AT84AD001BCTD ATMEL [ATMEL Corporation], AT84AD001BCTD Datasheet - Page 41

• Manufacturer Part Number: AT84AD001BCTD
• Description: Dual 8-bit 1 Gsps ADC
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 44. Write Chronogram
2153C–BDC–04/04
Internal register
value
Mode
sdata
sldn
sclk
Reset
Reset setting
1
a[2]
•
•
It is possible to have only one clock cycle with “sldn” at 1 between two following write
procedures.
•
To reset the registers, the Pin mode can be used as a reset pin for chip initialization,
even when the 3-wire serial interface is used.
Figure 45. Timing Definition
A minimum of one clock cycle with “sldn” returned at 1 is requested to close the
write procedure and make the interface ready for a new write procedure. Any clock
cycle where “sldn” is at 1 before the write procedure is completed interrupts this
procedure and no further data transfer to the internal registers is performed.
Additional clock cycles with “sldn” at 0 after the parallel data transfer to the register
(done at the 20th consecutive clock cycle with “sldn” at 0) do not affect the write
procedure and are ignored.
16 bits of data must always be entered even if the internal addressed register has
less than 16 bits. Unused bits (usually MSBs) are ignored. Bit signification and bit
positions for the internal registers are detailed in Table 12 on page 37.
a[1]
2
a[0] d[15]
3
Mode
sdata
sldn
sclk
4
5
Twlmode
Write procedure
Tdmode
d[8]
Tssdata
Tssldn
d[7]
13
Thsdata
Thsldn
d[6]
14
d[5]
Tsclk
15
d[4]
Twsclk
16
d[3]
17
d[2]
AT84AD001B
18
Tdmode
d[1]
19
d[0]
20
New d
41