AT84AD001BCTD ATMEL [ATMEL Corporation], AT84AD001BCTD Datasheet - Page 54
AT84AD001BCTD
Manufacturer Part Number
AT84AD001BCTD
Description
Dual 8-bit 1 Gsps ADC
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT84AD001BCTD.pdf
(60 pages)
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Figure 60. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused)
Note:
Using the Dual ADC With
and ASIC/FPGA Load
54
If the outputs are to be used in single-ended mode, it is recommended that the true and false signals be terminated with a 50Ω
resistor.
AT84AD001B
Port B
Port A
DOBI0 / DOBI0N
DOBI1 / DOBI1N
DOBI2 / DOBI2N
DOBI3 / DOBI3N
DOBI4 / DOBI4N
DOBI5 / DOBI5N
DOBI6 / DOBI6N
DOBI7 / DOBI7N
DOAI0 / DOAI0N
DOAI1 / DOAI1N
DOAI2 / DOAI2N
DOAI3 / DOAI3N
DOAI4 / DOAI4N
DOAI5 / DOAI5N
DOAI6 / DOAI6N
DOAI7 / DOAI7N
Figure 61 on page 55 illustrates the configuration of the dual ADC (1:2 DMUX mode,
independent I and Q clocks) driving an LVDS system (ASIC/FPGA) with potential addi-
tional DMUXes used to halve the speed of the dual ADC outputs.
Floating (High Z)
Dual ADC Package
VCCO
DOAI0N
DOAI0
Z0 = 50Ω
Z0 = 50Ω
LVDS In
LVDS In
100Ω
2153C–BDC–04/04
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