ADSP-21262_05 AD [Analog Devices], ADSP-21262_05 Datasheet - Page 21

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ADSP-21262_05

Manufacturer Part Number
ADSP-21262_05
Description
Embedded Processor
Manufacturer
AD [Analog Devices]
Datasheet
Timer PWM_OUT Cycle Timing
The timing specification in
Timer PWM_OUT (pulse-width modulation) mode. Timer sig-
nals are routed to the DAI_P20–1 pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20–1 pins.
Table 14. Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The timing specification in
Timer WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 15. Timer Width Capture Timing
Parameter
Switching Characteristic
t
Parameter
Timing Requirement
t
PWMO
PWI
DAI_P20–1
DAI_P20–1
(TIMER)
(TIMER)
Timer Pulse Width Output
Timer Pulse Width
Table 14
Table 15
and
and
Figure 12
Figure 13
Figure 13. Timer Width Capture Timing
Rev. B | Page 21 of 48 | August 2005
applies to
applies to
Figure 12. Timer PWM_OUT Timing
Min
2 t
Min
2 t
CCLK
CCLK
t
PWMO
– 1
t
PWI
Max
2(2
Max
2(2
31
31
– 1) t
– 1) t
CCLK
CCLK
ADSP-21262
Unit
ns
Unit
ns

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