ADSP-21262_05 AD [Analog Devices], ADSP-21262_05 Datasheet - Page 25

• Manufacturer Part Number: ADSP-21262_05
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Memory Read—Parallel Port
The specifications in
Figure 18
memory-mapped peripherals) when the ADSP-21262 is access-
ing external memory space.
Table 19. 8-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
D = (data cycle duration) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
DAD
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
ADRH
CCLK
(if a hold cycle is specified, else H = 0)
are for asynchronous interfacing to memories (and
Address/Data7–0 Setup Before RD High
Address/Data7–0 Hold After RD High
Address 15–8 to Data Valid
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data15–0 Setup Before ALE Deasserted
Address/Data15–0 Hold After ALE Deasserted
ALE Deasserted
RD Pulse Width
Address/Data15–8 Hold After RD High
AD15-8
AD7-0
Table
ALE
WR
RD
19,
CCLK
Table
1
to Address/Data7–0 in High Z
20,
Figure
VALID ADDRESS
VALID ADDRESS
t
ADAS
t
ALEW
17, and
Rev. B | Page 25 of 48 | August 2005
Figure 17. 8-Bit Memory Read Cycle
t
ADAH
t
ALEHZ
1
t
ALERW
1
Min
3.3
0
2 × t
1 × t
2.5 × t
0.5 × t
0.5 × t
D – 2
0.5 × t
CCLK
CCLK
t
DAD
CCLK
CCLK
CCLK
CCLK
VALID ADDRESS
– 2
– 0.5
– 2.0
– 0.8
– 0.8
– 1 + H
t
VALID DATA
RW
t
DRS
t
t
DRH
ADRH
Max
D + 0.5 × t
0.5 × t
CCLK
+ 2.0
CCLK
– 3.5
ADSP-21262
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns