ADSP-21266_07 AD [Analog Devices], ADSP-21266_07 Datasheet - Page 16

• Manufacturer Part Number: ADSP-21266_07
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-21266
PACKAGE INFORMATION
The information presented in
the package branding for the ADSP-21266 processors. For a
complete listing of product availability, see
Page
Table 8. Package Brand Information
ESD CAUTION
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 9. Absolute Maximum Ratings
Brand Key
t
pp
Z
cc
vvvvvv.x
n.n
yyww
Parameter
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage –0.5 V to V
44.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Figure 5. Typical Package Brand
yyww country_of_origin
S
a
DDEXT
ADSP-2126x
vvvvvv.x n.n
Field Description
Temperature Range
Package Type
RoHS Compliant Option (optional)
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
tppZ-cc
Figure 5
VDD
DDEXT
DDINT
)
Table 9
)
)
provides details about
Rating
–0.3 V to +1.4 V
–0.3 V to +1.4 V
–0.3 V to +3.8 V
+0.5 V
Ordering Guide on
may cause perma-
Rev. C | Page 16 of 44 | October 2007
Table 9. Absolute Maximum Ratings
TIMING SPECIFICATIONS
The ADSP-21266’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP’s internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLK_CFG1–0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The ADSP-21266’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Figure 6
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2126x SHARC DSP Core
Manual.
The VCO frequency is calculated as follows:
where:
f
PLLM = multiplier value programmed.
f
f
f
Note the definitions of various clock periods shown in
which are a function of CLKIN and the appropriate ratio con-
trol shown in
In
f
where:
f
PLLM = Multiplier value programmed
PLLN = Divider value programmed.
f
VCO
INPUT
INPUT
INPUT
CCLK
CCLK
Parameter
Output Voltage Swing –0.5 V to V
Load Capacitance
Storage Temperature Range
Junction Temperature Under Bias
VCO
Table
= VCO frequency.
= 2 × PLLM × f
= CCLK frequency
= (2 × PLLM × f
= input frequency to the PLL.
= CLKIN when the input divider is disabled.
= CLKIN/2 when the input divider is enabled.
shows core to CLKIN relationships with external oscil-
11, CCLK is defined as:
Table
11.
INPUT
INPUT
)
÷
(2 × PLLN)
DDEXT
Rating
+0.5 V
200 pF
–65°C to +150°C
125°C
Table 10