ADMC328TN AD [Analog Devices], ADMC328TN Datasheet - Page 13

• Manufacturer Part Number: ADMC328TN
• Description: 28-Lead ROM-Based DSP Motor Controller with Current Sense
• Manufacturer: AD [Analog Devices]

Width of the PWMSYNC Pulse: PWMSYNCWT Register
The PWM controller of the ADMCF328 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM frequency
in the double update mode. This PWMSYNC synchronizes
the operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT register. The width of the PWMSYNC pulse,
T
which means that the width of the pulse is programmable from t
to 256 t
of 20 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is 2.0 s.
PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
Registers
The duty cycles of the six PWM output signals are controlled
by the three duty cycle registers, PWMCHA, PWMCHB, and
PWMCHC. The integer value in the register PWMCHA controls
the duty cycle of the signals on AH and AL. PWMCHB controls
the duty cycle of the signals on BH and BL, and PWMCHC
controls the duty cycle of the signals on CH and CL. The duty
cycle registers are programmed in integer counts of the funda-
mental time unit, t
high-side PWM signal produced by the three-phase timing unit
over half the PWM period. The switching signals produced by
the three-phase timing unit are also adjusted to incorporate the
programmed dead time value in the PWMDT register.
The PWM is center-based. This means that in single update mode
the resulting output waveforms are symmetrical and centered in
the PWMSYNC period. Figure 7 presents a typical PWM tim-
ing diagram illustrating the PWM-related registers’ (PWMCHA,
PWMTM, PWMDT, and PWMSYNCWT) control over the
waveform timing in both half cycles of the PWM period. The
magnitude of each parameter in the timing diagram is determined
by multiplying the integer value in each register by t
50 ns). It may be seen in the timing diagram how dead time is
incorporated into the waveforms by moving the switching edges
away from the instants set by the PWMCHA register.
Each switching edge is moved by an equal amount (PWMDT
pulse, whose width is set by the PWMSYNCWT register, is also
shown. Bit 3 of the SYSSTAT register indicates which half cycle
is active. This can be useful in double update mode, as will be
discussed later.
REV. B
SYSSTAT (3)
PWMSYNC
Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode
t
PWMSYNC
CK
) to preserve the symmetrical output patterns. The PWMSYNC
CK
AH
AL
, is given by:
(corresponding to 50 ns to 12.8 s for a CLKOUT rate
T
PWMSYNC
2
PWMDT
CK
PWMTM
, and define the desired on-time of the
t
CK
PWMCHA
PWMSYNCWT
PWMCHA
PWMSYNCWT + 1
PWMTM
2
1
CK
PWMDT
(typically
CK
–13–
The resultant on-times of the PWM signals shown in Figure 7
may be written as:
The corresponding duty cycles are:
Obviously, negative values of T
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
T
The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode. Addi-
tionally, it is seen that the dead time is inserted into the PWM
signals in the same way as in the single update mode.
In general, the on-times of the PWM signals in double update
mode are defined by:
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
SYSSTAT (3)
S
Figure 8. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode
PWMSYNC
, corresponding to a 100% duty cycle.
T
T
T
T
AH
AL
AH
AL
d
d
AH
AL
AH
= (PWMTM
AL
= (PWMCHA
– PWMCHA
2
2
– PWMDT
2
T
T
T
T
AL
(
AH
S
(
PWMDT
PWMSYNCWT
S
PWMTM
PWMCHA
PWMTM
PWMTM
1
PWMCHA
1
+ PWMTM
1
2
2
+ PWMCHA
)
1
– PWMDT
PWMCHA
1
–
+ 1
t
CK
PWMTM
–
PWMCHA
PWMDT
–
1
AH
–
PWMCHA
2
PWMTM
PWMCHA
– PWMCHA
1
PWMDT
and T
– PWMDT
2
– PWMDT
)
–
2
AL
PWMTM
PWMDT
PWMSYNCWT
t
ADMC328
are not permitted
CK
–
2
1
PWMDT
) t
2
1
2
CK
PWMDT
)
2
+ 1
t
CK
2