ADMC328TN AD [Analog Devices], ADMC328TN Datasheet - Page 14

• Manufacturer Part Number: ADMC328TN
• Description: 28-Lead ROM-Based DSP Motor Controller with Current Sense
• Manufacturer: AD [Analog Devices]

ADMC328
because for the completely general case in double update mode,
the switching period is given by:
Again, the values of T
zero and T
PWM signals similar to those illustrated in Figure 7 and Figure
8 can be produced on the BH, BL, CH, and CL outputs by pro-
gramming the PWMCHB and PWMCHC registers in a manner
identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM register is written
after the PWMCHA, PWMCHB, and PWMCHC registers,
then the first PWMSYNC pulse (and interrupt if enabled) will
be generated (1.5
write to the PWMTM register in single update mode. In double
update mode, the first PWMSYNC pulse will be generated
(t
register in single update mode.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 t
CLKOUT) since incrementing one of the duty cycle registers by
one changes the resultant on-time of the associated PWM sig-
nals by t
In double update mode, improved resolution is possible since
different values of the duty cycles registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of t
PWM resolution of t
20 MHz CLKOUT).
The achievable PWM switching frequency at a given PWM
resolution is tabulated in Table IV.
CK
PWMTM) seconds after the initial write to the PWMTM
CK
d
d
S
AH
AL
in each half period (or 2 t
.
T
–
T
S
T
T
T
PWMTM
PWMCHA
PWMTM
PWCHA
= (PWMTM
AL
PWMDT
AH
S
PWMTM
S
CK
t
CK
AH
PWMTM
in double update mode (or 50 ns for a
PWMTM
and T
CK
2
1
1
PWMTM) seconds after the initial
1
. This corresponds to an effective
1
1
PWMDT
1
PWMDT
PWMTM
PWMTM
AL
PWMCHA
PWMTM
+ PWMTM
1
are constrained to lie between
1
CK
PWMTM
CK
PWMTM
(or 100 ns for a 20 MHz
1
2
for the full period).
2
2
2
PWMDT
2
2
PWMCHA
)
2
t
2
CK
2
1
–14–
Table IV. Achievable PWM Resolution in Single and Double
Update Modes
Resolution
(Bit)
8
9
10
11
12
Minimum Pulsewidth: PWMPD Register
In many power converter switching applications, it is desirable
to eliminate PWM switching pulses shorter than a certain width.
It takes a finite time to both turn on and turn off modern power
semiconductor devices. Therefore, if the width of any of the PWM
pulses is shorter than some minimum value, it may be desirable to
completely eliminate the PWM switching for that particular cycle.
The allowable minimum on-time for any of the six PWM out-
puts for half a PWM period that can be produced by the PWM
controller may be programmed using the PWMPD register. The
minimum on-time is programmed in increments of t
the minimum on-time that will be produced for any half PWM
period, T
A PWMPD value of 0x002 defines a permissible minimum
on-time of 100 ns for a 20 MHz CLKOUT.
In each half cycle of the PWM, the timing unit checks the on-
time of each of the six PWM signals. If any of the times is found
to be less than the value specified by the PWMPD register, the
corresponding PWM signal is turned OFF for the entire half
period, and its complementary signal is turned completely ON.
Consider the example where PWMTM = 200, PWMCHA = 5,
PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz
while operating in single update mode. For this case, the PWM
switching frequency is 50 kHz and the dead time is 300 ns. The
minimum permissible on-time of any PWM signal over one-half
of any period is 500 ns. Clearly, for this example, the dead-time
adjusted on-time of the AH signal for one-half a PWM period is
(5–3)
permissible value, output AH of the timing unit will remain
OFF (0% duty cycle). Additionally, the AL signal will be turned
ON for the entire half period (100% duty cycle).
Output Control Unit: PWMSEG Register
The operation of the output control unit is managed by the 9-bit
read/write PWMSEG register. This register sets two distinct
features of the output control unit that are directly useful in the
control of ECM or BDCM.
The PWMSEG register contains three crossover bits, one for each
pair of PWM outputs. Setting Bit 8 of the PWMSEG register
enables the crossover mode for the AH/AL pair of PWM signals;
setting Bit 7 enables crossover on the BH/BL pair of PWM signals;
and setting Bit 6 enables crossover on the CH/CL pair of PWM
signals. If crossover mode is enabled for any pair of PWM signals,
the high-side PWM signal from the timing unit (for example
AH) is diverted to the associated low-side output of the output
control unit so that the signal will ultimately appear at the AL
pin. Of course, the corresponding low-side output of the timing
unit is also diverted to the complementary high-side output of
50 ns = 100 ns. Because this is less than the minimum
MIN
, is related to the value in the PWMPD register by:
Single Update Mode
PWM Frequency (kHz)
39.1
19.5
9.8
4.9
2.4
T
MIN
= PWMPD
Double Update Mode
PWM Frequency (kHz)
78.1
39.1
19.5
9.8
4.9
t
CK
CK
so that
REV. B