ADMC328TN AD [Analog Devices], ADMC328TN Datasheet - Page 17

• Manufacturer Part Number: ADMC328TN
• Description: 28-Lead ROM-Based DSP Motor Controller with Current Sense
• Manufacturer: AD [Analog Devices]

Following reset, V
conversion process are initiated by the PWMSYNC pulse, as
shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be
programmed according to Figure 13 to ensure complete resetting.
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMC328 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over an approximately 20% cur-
rent range.
The ADC system consists of four comparators and a single timer,
which may be clocked at either the DSP rate or half the DSP
rate depending on the setting of the ADCCNT bit (Bit 7) of the
MODECTRL register. When this bit is cleared, the timers count
at a slower rate of CLKIN. When this bit is set, they count at
CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,
and ADCAUX are the registers that capture the conversion times,
which are effectively the timer value when the associated com-
parator trips.
ADC Resolution
The ADC is intrinsically linked to the PWM block through the
PWMSYNC pulse controlling the ADC conversion process.
Because of this link, the effective resolution of the ADC is a
REV. B
COMPARATOR
PWMSYNC
OUTPUT
V
VIL
200
150
100
50
0
Figure 13. PWMSYNCWT Program Value
Figure 12. Analog Input Block Operation
0
C
2
= 0 at t = 0. This reset and the start of the
t
T
VIL
PWM
CHARGING CAPACITOR – nF
–T
CRST
V
C
4
6
V
T
CMAX
CRST
8
10
t
V1
–17–
function of both the PWM switching frequency and the rate at
which the ADC counter timer is clocked. For a CLKOUT period
of t
ADC is given by:
Where T
update mode, or it is equal to half that period if operating in
double update mode. For an assumed CLKOUT frequency of
20 MHz and PWMSYNC pulsewidth of 2.0 s, the effective
resolution of the ADC block is tabulated for various PWM
switching frequencies in Table VII.
PWM
Freq.
(kHz)
2.4
4
8
18
25
Charging Capacitor Selection
The charging capacitor value is selected based on the sample
(PWM) frequency desired. A selected capacitor value that is
too small will reduce the available resolution of the ADC by
having the ramp voltage rise rapidly and convert too quickly,
not utilizing all possible counts available in the PWM cycle. Too
large a capacitor may not convert in the available PWM cycle,
returning 0xFFF. To select a charging capacitor use Figure 14,
select the sampling frequency desired, then determine if the cur-
rent source is to be tuned to a nominal 100 A or left in the
default (0x0 code) trim state, then determine the proper charge
capacitor from the appropriate curve.
CK
and a PWM period of T
100
10
Max Count = min (4095, (T
PWM
1
Max Count = min (4095, (T
1
Figure 14. Timing Capacitor Selection
MODECTRL[7] = 0
Max
Count
4095
2480
1230
535
380
Table VII. ADC Resolution Examples
DEFAULT ICONST
is equal to the PWM period if operating in single
for MODECTRL Bit 7 = 0
for MODECTRL Bit 7 = 1
Effective
Resolution
12
>11
>10
>9
>8
TUNED ICONST
FREQUENCY – kHz
PWM
10
, the maximum count of the
PWM
PWM
– T
MODECTRL[7] = 1
Max
Count
4095
4095
2460
1070
760
– T
CRST
ADMC328
CRST
)/2 t
)/t
Effective
Resolution
12
12
>11
>10
>9
CK
CK
)
)
100