XC3S100E-4CP132C XILINX [Xilinx, Inc], XC3S100E-4CP132C Datasheet - Page 139

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XC3S100E-4CP132C

Manufacturer Part Number
XC3S100E-4CP132C
Description
Spartan-3E FPGA Family
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
User I/Os by Bank
Table 13
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package
Table 14: User I/Os Per Bank for the XC3S250E in TQ144 Package
18
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
Package
Package
Bank
Edge
Edge
and
DONE
PROG_B
TCK
TDI
TDO
TMS
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
Table 14
I/O Bank
I/O Bank
XC3S100E Pin Name
0
1
2
3
0
1
2
3
indicate how the 108 available
Maximum
Maximum
108
108
I/O
I/O
26
28
26
28
26
28
26
28
DONE
PROG_B
TCK
TDI
TDO
TMS
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
I/O
I/O
13
22
11
20
9
0
0
9
0
0
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XC3S250E Pin Name
INPUT
INPUT
19
21
6
5
4
6
6
5
4
4
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
21
20
42
21
20
42
1
0
1
0
TQ144 Pin
P110
P144
P109
P108
P102
P137
P115
P72
P30
P65
P45
P80
P1
P9
Advance Product Specification
DS312-4 (v1.1) March 21, 2005
VREF
VREF
2
2
2
3
9
2
2
2
3
9
VCCAUX
VCCAUX
VCCAUX
VCCAUX
CONFIG
CONFIG
VCCINT
VCCINT
VCCINT
VCCINT
JTAG
JTAG
JTAG
JTAG
Type
GCLK
GCLK
16
16
8
0
0
8
8
0
0
8
R

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