XC3S100E-4CP132C XILINX [Xilinx, Inc], XC3S100E-4CP132C Datasheet - Page 97
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XC3S100E-4CP132C
Manufacturer Part Number
XC3S100E-4CP132C
Description
Spartan-3E FPGA Family
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
1.XC3S100E-4CP132C.pdf
(193 pages)
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Functional Description
90
instruction
JPROG
Figure 65: Boundary-Scan Configuration Flow Diagram
Load
No
Yes
and V
(JTAG port becomes
Load configuration
and V
INIT_B = High?
www.xilinx.com
(Clock five 1's
Load JSTART
Load CFG_IN
Synchronous
Reconfigure?
configuration
data frames
User mode
Power-On
V
Yes
instruction
instruction
TAP reset
sequence
mode pins
CCO
Yes
Yes
available)
on TMS)
Start-Up
correct?
CCINT
memory
Sample
CCAUX
Clear
CRC
Bank 4 > 1V
>1V
> 2V
No
No
No
INIT_B goes Low.
Abort Start-Up
Yes
Set PROG_B Low
after Power-On
PROG_B = Low
DS312-2_59_022505
No
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
R
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