XC3S100E-4CP132C XILINX [Xilinx, Inc], XC3S100E-4CP132C Datasheet - Page 53

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XC3S100E-4CP132C

Manufacturer Part Number
XC3S100E-4CP132C
Description
Spartan-3E FPGA Family
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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Functional Description
The Variable Phase Mode
The Variable Phase mode dynamically adjusts the fine
phase shift over time using three inputs to the PS compo-
Table 30: Signals for Variable Phase Mode
46
Notes:
1.
PSEN
PSCLK
PSINCDEC
PSDONE
It is possible to program this input for either a true or inverted polarity.
Signal
(1)
(1)
a. CLKOUT_PHASE_SHIFT = NONE
b. CLKOUT_PHASE_SHIFT = FIXED
c. CLKOUT_PHASE_SHIFT = VARIABLE
(1)
Input
Input
Input
Output
Shift Range over all N Values:
Shift Range over all P Values:
Shift Range over all P Values:
Direction
CLKFB before
CLKFB after
Enables PSCLK for variable phase adjustment.
Clock to synchronize phase shift adjustment.
Chooses between increment and decrement for phase adjustment. It is
synchronized to the PSCLK signal.
Goes High to indicate that present phase adjustment is complete and PS component
is ready for next phase adjustment request. It is synchronized to the PSCLK signal.
Increment
Increment
CLKIN
CLKFB
CLKIN
CLKFB
CLKIN
Figure 41: Phase Shifter Waveforms
www.xilinx.com
–255
–255
nent (PSEN, PSCLK, and PSINCDEC), as defined in
Table
30.
0
0
Description
512
512
P
P
512
N
* T
* T
* T
CLKIN
CLKIN
CLKIN
+255
+255
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
DS312-2_61_021505
R

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