MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 19

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Data Transfer. A Transmit Interrupt is generated
each time the transmit buffer becomes empty. The
interrupt may be satisfied either by writing another
character into the transmit buffer or by resetting the
Transmit Interrupt Pending latch with a Reset Tx In-
terrupt Pending command. If the interrupt is satisfied
with this command, and nothing more is written into
the transmit buffer, there can be no further Transmit
Interrupts due to a Buffer Empty condition, because
it is the process of the buffer becoming empty that
causes the interrupts. This situation does cause a
Transmit Underrun condition when the data in the
shift register is shifted out.
Another way of detecting when the transmitter re-
quires service is to poll the Tx Buffer Empty bit in Sta-
tus Register 0. This bit is set to a one every time the
data in the transmit buffer is downloaded into the
transmit shift register. When data is written to the
transmit buffer, this bit is reset to zero.
The SIO has all the signals and controls necessary
to implement a DMA transfer routine for the trans-
mitter. The routine may be configured to enable the
DMA controller, after the first character is written to
the transmit buffer, and then using the TxRDY out-
put pin to signal the DMA that the transmitter re-
quires service. If a data character is not loaded into
the transmit buffer by the time the transmit shift re-
gister is empty, the SIO enters the Transmit Under-
run condition.
Transmit Underrun/End of Message. When the
transmitter has no further data to transmit, the SIO
inserts filler characters to maintain synchronization.
The SIO has two programmable options for handling
this situation : sync characters can be inserted, or
the CRC characters generated so far can be sent,
followed by sync characters. These options are con-
trolled by the state of the Transmit Underrun/EOM
Latch in Status Register 0.
Following a hardware or software reset, the Trans-
mit Underrun/EOM Latch is set to a one. This allows
sync characters to be inserted when there is no data
to send. CRC is not calculated on the automatically
inserted sync characters. To allow CRC
characters to be sent when the transmitter has no
data, the Transmit Underrun/EOM Latch must be re-
set to zero. This latch is reset by issuing a Reset Tx
Underrun/EOM Latch command in the Command
Register. Following the CRC characters, the SIO
sends sync characters to terminate the message.
There is no restriction as to when, in the message,
the Transmit Underrun/EOM Latch can be reset, but
once the reset command is issued, the 16-bit CRC
is sent and followed by sync characters the first time
the transmitter has no data to send. A Transmit Un-
derrun condition will cause an External/Status Inter-
rupt to be generated whenever the Transmit Under-
run/EOM Latch is set.
For sync character insertion only, at the termination
of a message, a Transmit Interrupt is generated only
after the first automatically inserted sync character
is loaded into the transmit shift register. The status
bits in Status Register 0 indicate that the Transmit
Underrun/EOM Latch and the Tx Buffer Empty bit
are set.
For CRC insertion, followed by sync characters, at
the termination of a message, the Transmit Under-
run/EOM Latch is set, and the Tx Buffer Empty bit
is reset while the CRC characters are being sent.
When the CRC characters are completely transmit-
ted, the Tx Buffer Empty status bit is set, and a
Transmit Interrupt is generated, indicating to the
CPU that another message can begin. This Trans-
mit Interrupt occurs when the first sync character
following the CRC characters is loaded into the
transmit shift register. If no more messages are to
be transmitted, the program can terminate transmis-
sion by disabling the transmitter.
CRC Generation. Setting the Tx CRC Enable bit in
the Transmit Control Register initiates CRC accu-
mulation when the program sends the first data
character to the SIO. To ensure CRC is calculated
correctly on each message, the Reset Tx CRC Gen-
erator command should be issued before the first
data character of the message is sent to the SIO.
The Tx CRC Enable bit can be changed on the fly
at any point in the message to include or exclude a
particular data character from CRC accumulation.
The Tx CRC Enable bit should be in the desired
state when the data character is loaded from the
transmit data buffer into the transmit shift register.
To ensure this bit is in the proper state, the Tx CRC
Enable bit should be loaded before sending the data
character to the SIO.
Transmit Termination. The SIO is equipped with a
special termination feature that maintains data inte-
grity and validity. If the transmitter is disabled (by re-
setting the Transmit Enable bit or using the Tx Auto
Enable signal) while a data or sync character is
being transmitted, the character is transmitted as u-
sual but is followed by a marking line instead of sync
or CRC characters. When the transmitter is disa-
bled, a character in the transmit buffer remains in the
buffer. If the transmitter is disabled while CRC char-
acters are being transmitted, the 16-bit transmission
is completed, but the remaining bits of the CRC
characters are replaced by sync characters.
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