MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 32

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

D5 : Transmit Auto Enables
When this bit is set to a one, and the Transmit Ena-
ble bit is also set, a Low on the CTS input pin will en-
able the transmitter. When this bit is zero, the CTS
pin is simply an input to the SIO, and its status is dis-
played in Status Register 0.
D4 : Send Break
When set to a one, this bit immediately forces the
Transmit Data output pin (TxD) to a spacing condi-
tion (continuous 0’s), regardless of any data being
transmitted at the time. This bit functions, whether
the transmitter is enabled or not. When this bit is re-
set to zero, the transmitter will continue to send the
contents of the transmit shift register. The shift re-
gister may contain sync characters, data characters,
or all ones.
D3 : Transmitter CRC Enable
This bit determines if CRC calculations are perfor-
med on a transmitted data character. If this bit is a
one at the time a character is loaded from the trans-
mit buffer to the transmit shift register, CRC is cal-
culated on the character. CRC is not calculated on
any automatically inserted sync characters. CRC is
not automatically appended to the end of a message
unless this bit is set, and the Transmit Under-
run/EOM status bit in Status Register 0 is reset when
a Transmit Underrun condition occurs. If this bit is a
zero when a character is loaded from the transmit
buffer into the transmit shift register, no CRC calcu-
lations are performed on the character. This bit is i-
gnored in Asynchronous modes.
D2 : Data Terminal Ready (DTR)
This is the control bit for the DTR output pin. When
this bit is set to a one, the DTR pin goes Low : when
this bit is reset to a zero, the DTR pin goes High.
D1 : Request To Send (RTS)
This is the control bit for the RTS output pin. In Syn-
chronous modes, when this bit is set to a one, the
RTS pin goes Low ; when this bit is reset to a zero,
the RTS pin goes High. In Asynchronous modes,
when this bit is set, the RTS pin goes Low ; when
this bit is reset, the RTS pin will go High only after
all the bits of the character are transmitted, and the
transmit buffer is empty.
D0 : Transmitter Enable
Data is not transmitted until this bit is set to a one,
until the Send Break bit is reset and, if Tx Auto En-
ables mode is selected, until the CTS pin is Low. To
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transmit sync or flag characters in Synchronous
modes, this bit has to be set when the transmit buffer
is empty. Data or sync characters in the process of
being transmitted are completely sent if this bit is re-
set to zero after transmission has started. If this bit
is reset during the transmission of a CRC character,
sync or flag characters are sent instead of the CRC
character.
STATUS REGISTER 0 (STAT 0)
READ ONLY
This register contains the status of the receive and
transmit buffers and the status bits for the five
sources of External/Status interrupts.
D7 : Break/Abort
This bit is reset by a channel or hardware reset. In
Asynchronous modes, this bit is set when a Break
sequence (null character plus framing error) is de-
tected in the received data stream. An External/Sta-
tus interrupt, if enabled, is generated when Break is
detected. The interrupt service routine must issue a
Reset
(Command 2) to the SIO, so the break detection lo-
gic can recognize the termination of the Break se-
quence.
The Break/Abort bit is reset to a zero when the ter-
mination of the Break sequence is detected in the in-
coming data stream. The termination of the Break
sequence also causes the generation of an Exter-
nal/Status interrupt. Command 2 must be issued to
enable the break detection logic to look for the next
Break sequence. A single extraneous null character
is present in the receiver after the termination of a
break ; it should be read and discarded.
In SDLC mode, this bit is set by the detection of an
Abort sequence (seven or more ones) in the recei-
ved data stream. The External/Status Interrupt is
handled the same way as in the case of a Break se-
quence. The Break/Abort bit is not used in the other
Synchronous modes.
D6 : Transit Underrun/EOM
This bit is set to a one following a hardware or chan-
nel reset, when the transmitter is disabled or when
a Send Abort command (Command 1) is issued.
This bit can only be reset by the Reset Transmit Un-
derrun/EOM Latch command in the Command Re-
gister. This bit is used to control the transmission of
BREAK/
ABORT
D 7
UNDERRUN
/EOM
D6
External/Status
CTS HUNT/
D5
SYNC
D4
DCD TX BUFR
D3
Interrupt
EMPTY
D2
PENDING
INTERPT
D1
command
CHAR
AVAIL
D0
RX