CY8C20X36A CYPRESS [Cypress Semiconductor], CY8C20X36A Datasheet - Page 11

• Manufacturer Part Number: CY8C20X36A
• Description: CapSense Applications Operating Range: 1.71 V to 5.5 V
• Manufacturer: CYPRESS [Cypress Semiconductor]

32-Pin QFN
Table 5. Pin Definitions – CY8C20436A, CY8C20446A, CY8C20466A PSoC Device
Document Number: 001-54459 Rev. *E
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
Pin
No.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
13. The center pad (CP) on the QFN package must be connected to ground (V
14. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
15. Alternate SPI clock.
it must be electrically floated and not connected to any other signal.
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
Digital
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOH
IOH
IOH
IOH
IOH
IOH
IOH
IOH
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
Power
Power
Type
Input
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
V
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
V
P0[7]
P0[5]
P0[3]
V
V
Name
SS
DD
SS
SS
Integrating input
Crystal output (XOut)
Crystal input (XIn)
I
I
SPI CLK.
ISSP CLK
Ground connection.
ISSP DATA
SPI CLK
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull-down
Supply voltage
Integrating input
Ground connection
Center pad must be connected to
ground
2
2
C SCL, SPI SS
C SDA, SPI MISO
[15]
[14]
Description
[14]
, I
, I
2
C SCL, SPI MOSI.
2
C SDA,
SS
) for best mechanical, thermal, and electrical performance. If not connected to ground,
AI, I2 C SCL, SPI SS, P1[7]
Figure 6.
AI , XOut, P2[5]
AI, XIn, P2[3]
CY8C20436A, CY8C20446A, CY8C20466A
AI, P0[1]
AI, P2[7]
AI, P2[1]
AI, P3[3]
AI, P3[1]
CY8C20X36A/46A/66A/96A
[13]
PSoC Device
1
2
3
4
5
6
7
8
( Top View )
QFN
24
23
22
21
20
19
18
17
Page 11 of 43
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
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