MPC8358 FREESCALE [Freescale Semiconductor, Inc], MPC8358 Datasheet - Page 50

• Manufacturer Part Number: MPC8358
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

I
Figure 32
Figure 33
50
All values refer to V
2
C
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
SDA
SCL
(reference)(state)
t
the t
time that the data with respect to the start condition (S) went invalid (X) relative to the t
to the low (L) state or hold time. Also, t
stop condition (P) reaching the valid state (V) relative to the t
setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
bridge the undefined region of the falling edge of SCL.
MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1
I2DVKH
B
= capacitance of one bus line in pF.
I2C
provides the AC test load for the I
shows the AC timing diagram for the I
S
symbolizes I
clock reference (K) going to the high (H) state or setup time. Also, t
IH
(min) and V
t
I2CF
for inputs and t
t
I2CL
t
I2SXKL
I2DVKH
Output
2
C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to
Parameter
IL
has only to be met if the device does not stretch the LOW period (t
Table 44. I
(max) levels (see
(first two letters of functional block)(reference)(state)(signal)(state)
Figure 33. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
I2PVKH
Figure 32. I
Table
Z
t
I2DVKH
0
= 50 Ω
symbolizes I
43).
t
2
I2CH
2
C.
C Bus AC Timing Diagram
2
t
I2SXKL
2
C bus.
C AC Test Load
2
C timing (I2) for the time that the data with respect to the
Symbol
t
t
I2PVKH
I2C
Sr
I2KHDX
t
V
V
I2CF
NH
NL
clock reference (K) going to the high (H) state or
t
I2SVKH
1
t
I2KHKL
R
L
(first two letters of functional block)(signal)(state)
= 50 Ω
20 + 0.1 C
0.1 × OV
0.2 × OV
I2SXKL
Min
0.6
1.3
symbolizes I
t
DD
DD
I2PVKH
for outputs. For example,
b
OV
4
I2C
IHmin
DD
t
I2CR
clock reference (K) going
I2CL
/2
of the SCL signal) to
2
Max
) of the SCL signal.
Freescale Semiconductor
300
C timing (I2) for the
—
—
—
—
P
t
I2CF
Unit
S
ns
μs
μs
V
V