PIC12F683-E/MD MICROCHIP [Microchip Technology], PIC12F683-E/MD Datasheet - Page 88

• Manufacturer Part Number: PIC12F683-E/MD
• Description: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC12F683
12.3.1
The on-chip POR circuit holds the chip in Reset until
V
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to V
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
V
Specifications” for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until V
reaches V
(BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to the Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
12.3.2
PIC12F683 has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to V
Figure 12-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the GP3/MCLR pin
becomes an external Reset input. In this mode, the
GP3/MCLR pin has a weak pull-up to V
DS41211D-page 86
DD
DD
Note:
has reached a high enough level for proper
is required. See Section 15.0 “Electrical
BOD
DD
POWER-ON RESET
The POR circuit does not produce an
internal Reset when V
re-enable the POR, V
for a minimum of 100 μs.
MCLR
. The use of an RC network, as shown in
(see Section 12.3.4 “Brown-Out Reset
DD
DD
must reach Vss
DD
declines. To
.
DD
. This
DD
FIGURE 12-2:
12.3.3
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.5 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
Configuration bit, PWRTE, can disable (if set) or enable
(if cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
due to:
• V
• Temperature variation
• Process variation
See
“Electrical Specifications”).
Note:
DD
(optional)
SW1
DC
variation
POWER-UP TIMER (PWRT)
Voltage spikes below V
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to V
parameters
V
DD
DD
R1
1 kΩ (or greater)
C1
0.1 μF
(optional, not critical)
to rise to an acceptable level. A
(needed with capacitor)
RECOMMENDED
CIRCUIT
© 2007 Microchip Technology Inc.
100 Ω
for
R2
Ω
should be used when
details
SS
MCLR
at the MCLR
(Section 15.0
PIC
MCU
MCLR
®
SS
.