PIC12F683-E/MD MICROCHIP [Microchip Technology], PIC12F683-E/MD Datasheet - Page 90

• Manufacturer Part Number: PIC12F683-E/MD
• Description: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC12F683
12.3.6
On power-up, the time-out sequence is as follows:
• PWRT time-out is invoked after POR has expired.
• OST is activated after the PWRT time-out has
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.7.2 “Two-Speed Start-up Sequence” and
Section 3.8 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F683 device
operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
TABLE 12-1:
TABLE 12-2:
TABLE 12-3:
DS41211D-page 88
XT, HS, LP
RC, EC, INTOSC
CONFIG
PCON
STATUS
Legend:
Note
Oscillator Configuration
Legend: u = unchanged, x = unknown
expired.
Name
POR
0
u
u
u
u
u
1:
2:
(2)
BOREN1 BOREN0
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 12-1) for operation of all register bits.
TIME-OUT SEQUENCE
Bit 9
BOR
x
0
u
u
u
u
TIME-OUT IN VARIOUS SITUATIONS
STATUS/PCON BITS AND THEIR SIGNIFICANCE
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Bit 8
TO
1
1
0
0
u
1
T
Bit 7
CPD
IRP
PWRT
—
PWRTE = 0
T
T
PWRT
OSC
PD
+ 1024 •
1
1
u
0
u
0
Bit 6
RP1
CP
—
Power-up
ULPWUE SBOREN
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
MCLRE
Bit 5
RP0
PWRTE = 1
1024 • T
PWRTE
—
Bit 4
TO
OSC
WDTE
12.3.7
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
Bit 0 is BOR (Brown-out). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0>
register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 4.2.4 “Ultra
Low-Power
“Brown-Out Reset (BOR)”.
Bit 3
PD
—
T
PWRT
PWRTE = 0
T
FOSC2
T
PWRT
Bit 2
OSC
+ 1024 •
—
Z
Brown-out Reset
POWER CONTROL (PCON)
REGISTER
Condition
FOSC1
Bit 1
POR
Wake-up”
DC
= 00 in the Configuration Word
PWRTE = 1
1024 • T
FOSC0
© 2007 Microchip Technology Inc.
Bit 0
BOR
C
—
OSC
and
--01 --qq
0001 1xxx
POR, BOR
Value on
—
Wake-up from
1024 • T
Section 12.3.4
DD
Sleep
--0u --uu
000q quuu
may have
—
Resets
Value on
all other
OSC
—
(1)