MPC8533E_10 FREESCALE [Freescale Semiconductor, Inc], MPC8533E_10 Datasheet - Page 7
MPC8533E_10
Manufacturer Part Number
MPC8533E_10
Description
Integrated Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MPC8533E_10.pdf
(112 pages)
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Three PCI Express interfaces
— Two ×4 link width interfaces and one ×1 link width interface
— PCI Express 1.0a compatible
— Auto-detection of number of connected lanes
— Selectable operation as root complex or endpoint
— Both 32- and 64-bit addressing
— 256-byte maximum payload size
— Virtual channel 0 only
— Traffic class 0 only
— Full 64-bit decode with 32-bit wide windows
Power management
— Supports power saving modes: doze, nap, and sleep
— Employs dynamic power management, which automatically minimizes power consumption of
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter-specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
— Burstiness feature that permits counting of burst events with a programmable time between
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE Std 1149.1™-compliant, JTAG boundary scan
783 FC-PBGA package
blocks when they are idle
bursts
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
MPC8533E Overview
7
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