A80960HA25SL2GX INTEL [Intel Corporation], A80960HA25SL2GX Datasheet - Page 13
A80960HA25SL2GX
Manufacturer Part Number
A80960HA25SL2GX
Description
80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.A80960HA25SL2GX.pdf
(102 pages)
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3.1
Advance Information
Table 6.
Pin Descriptions
This section defines the 80960Hx pins.
descriptions in
which can be driven active according to normal JTAG specifications.
Pin Description Nomenclature
Symbol
H(...)
B(...)
R(...)
S(E)
S(L)
A(E)
A(L)
I/O
O
I
-
Datasheet
Table
Input only pin.
Output only pin.
Pin can be input or output.
Pin must be connected as indicated for proper device functionality.
Synchronous edge sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
Synchronous level sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
Asynchronous edge-sensitive input.
Asynchronous level-sensitive input.
While the processor bus is in the HOLD state (HOLDA asserted), the pin:
While the processor is in the bus backoff state (BOFF asserted), the pin:
While the processor’s RESET pin is asserted, the pin:
H(1) is driven to V
H(0) is driven to V
H(Z) floats
H(Q) continues to be a valid output
B(1) is driven to V
B(0) is driven to V
B(Z) floats
B(Q) continues to be a valid output
R(1) is driven to V
R(0) is driven to V
R(Z) floats
R(Q) continues to be a valid output
7. All pins float while the processor is in the ONCE mode, except TDO,
CC
SS
CC
SS
CC
SS
Table 6
presents the legend for interpreting the pin
Description
80960HA/HD/HT
7
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