A80960HA25SL2GX INTEL [Intel Corporation], A80960HA25SL2GX Datasheet - Page 42

• Manufacturer Part Number: A80960HA25SL2GX
• Description: 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
• Manufacturer: INTEL [Intel Corporation]

80960HA/HD/HT
36
Table 23. AC Characteristics Notes
Table 24. 80960Hx Boundary Scan Test Signal Timings
NOTES:
10.Relative Output timings are not tested.
11.Not tested.
12.The processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for
T
T
T
T
T
T
T
T
T
T
T
T
T
T
NOTE:
1. See
2. See
3. See
4. Where N is the number of N
5. N = Number of wait states inserted with READY.
6. These specifications are guaranteed by the processor.
7. These specifications must be met by the system for proper operation of the processor.
8. RESET is an asynchronous input that has no required setup and hold time for proper operation. However,
9. The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times
1. Not tested.
BSF
BSC
BSCH
BSCL
BSCR
BSCF
BSIS1
BSIH1
BSOV1
BSOF1
BSOV2
BSOF2
BSIS2
BSIH2
Symbol
for output delays and hold times.
information for rise and fall times.
Controller Region Table. WAIT never goes active when there are no wait states in an access.
to guarantee the device exits the reset mode synchronized to a particular clock edge, the rising edge of
RESET must meet setup and hold times to the rising edge of the CLKIN.
for proper operation. These pins are sampled by the interrupt controller every clock and must be active for
at least two consecutive CLKIN rising edges when asserting them asynchronously. To guarantee
recognition at a particular clock edge, the setup and hold times shown must be met.
the following signals: A31:4, SUP, CT3:0, D/C, LOCK, W/R, BE3:0.
Section 4.8, “AC Timing Waveforms” on page 38
Figure 25 “Output Delay or Hold vs. Load Capacitance” on page 44
Figure 22 “Rise and Fall Time Derating at 85°C and Minimum V
TCK Frequency
TCK Period
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
Input Setup to TCK —
TDI, TMS
Input Hold from TCK —
TDI, TMS
TDO Valid Delay
TDO Float Delay
All Outputs (Non-Test)
Valid Delay
All Outputs (Non-Test)
Float Delay
Input Setup to TCK - All
Inputs (Non-Test)
Input Hold from TCK - All
Inputs (Non-Test)
Parameter
RAD
, N
RDD
, N
Min
125
WAD
40
40
10
10
0
8
3
3
8
or N
Infinite
WDD
Max
30
36
30
36
8
8
8
for waveforms and definitions.
wait states that are programmed in the Bus
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Advance Information
CC
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
(1)
Relative to TCK
Relative to TCK (1)
” on page 43
for capacitive derating information
for capacitive derating
Notes
Datasheet