MPC862 MOTOROLA [Motorola, Inc], MPC862 Datasheet - Page 2
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MPC862
Manufacturer Part Number
MPC862
Description
Hardware Specifications
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MPC862.pdf
(88 pages)
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Features
Features
Table 1 shows the functionality supported by the members of the MPC862/857T/857DSL family.
2
The following list summarizes the key MPC862/857T/857DSL features:
2
•
•
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
— Advanced on-chip-emulation debug mode
The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR.
The MPC862/857T/857DSL adds major new features available in “enhanced SAR” (ESAR) mode,
including the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— ATM port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
Features
– 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte
– 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
– Caches are physically addressed, implement a least recently used (LRU) replacement
spaces and 16 protection groups
1
2
MPC862P
MPC862T
MPC857T
MPC857DSL
On the MPC857DSL, the SCC (SCC1) is for ethernet only. Also, the MPC857DSL does
not support the Time Slot Assigner (TSA).
On the MPC857DSL, the SMC (SMC1) is for UART only.
instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative
with 128 sets.
cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
cache blocks.
algorithm, and are lockable on a cache block basis.
Part
MPC862/857T/857DSL Hardware Specifications
Freescale Semiconductor, Inc.
Instruction
For More Information On This Product,
16 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Cache
Table 1. MPC862 Family Functionality
Go to: www.freescale.com
Cache
Data Cache
8 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Up to 4
Up to 4
10T
1
1
Ethernet
10/100
1
1
1
1
SCC
1
4
4
1
1
SMC
1
2
2
2
2
MOTOROLA