DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 44
DP83256VF-AP
Manufacturer Part Number
DP83256VF-AP
Description
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83256VF-AP.pdf
(144 pages)
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D0 D1
D2 D3
D4 D5
D6
D7
5 0 Registers
5 2 CONFIGURATION REGISTER (CR)
The Configuration Register controls the Configuration Switch Block and enables disables both the A and B ports The CR can
be used to create a number of Configuration Loopback paths
The CR is conditionally writable because the TTCR can be writing a new value into the register if this feature is enabled
Note that the A Request and B Indicate port are offered only on the DP83257 and not in the DP83256 For further informa-
tion refer to section 3 4 CONFIGURATION SWITCH
ACCESS RULES
Bit
BIE
ADDRESS
D7
AIS0 AIS1
BIS0 BIS1
TRS0 TRS1
AIE
BIE
01h
Symbol
AIE
D6
(Continued)
A INDICATE SELECTOR
Configuration Switch data buses for the A Indicate output port (AIP AIC AID
AIS1
0
0
1
1
B INDICATE SELECTOR
Configuration Switch data buses for the B Indicate output port (BIP BIC BID
BIS1
0
0
1
1
Note Even though this bit can be set and or cleared in the DP83256 it will not affect any I Os since the DP83256 does not offer a
TRANSMIT REQUEST SELECTOR
the four Configuration Switch data buses for the input to the Transmitter Block
TRS1
0
0
1
1
Note If the PLAYER
A INDICATE ENABLE
0 Disables the A Indicate output port The A Indicate port pins will be tri-stated when the port is
1 Enables the A Indicate output port (AIP AIC AID
B INDICATE ENABLE
0 Disables the B Indicate output port The B Indicate port pins will be tri-stated when the port is
1 Enables the B Indicate output port (BIP BIC BID
Note Even though this bit can be set and or cleared in the DP83256 it will not affect any I Os since the DP83256 does not offer a
Always
disabled
disabled
READ
B Indicate port
Register (CTSR) are set to 00) and the PHY Invalid Bus is selected then the PLAYER
Halt symbol pairs and then continuous Idle symbols due to the Repeat Filter when in the Repeat state
B Indicate port
TRS1
D5
AIS0
0
1
0
1
BIS0
0
1
0
1
TRS0
0
1
0
1
PHY Invalid Bus
Receiver Bus
A Request Bus
B Request Bus
PHY Invalid Bus
Receiver Bus
A Request Bus
B Request Bus
PHY Invalid Bus
Receiver Bus
A Request Bus
B Request Bus
a
device is in Active Transmit Mode (i e the Transmit Mode bits (TM
Conditional
TRS0
WRITE
D4
k
k
0 1
0 1
l
l
BIS1
D3
k
The A Indicate Selector
The B Indicate Selector
0 1
44
l
The Transmit Request Selector
Description
BIS0
D2
k
k
7 0
7 0
l
l
)
)
AIS1
k
k
D1
0 1
0 1
l
l
bits selects one of the four
bits selects one of the four
k
2 0
a
device will transmit a maximum of four
l
AIS0
D0
) of the Current Transmit State
k
k
k
0 1
7 0
7 0
l
l
l
)
)
bits select one of
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