DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 93

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

Symbol
E RST
SP0
SP1
EP0
EP1
6 0 Signal Descriptions
MISCELLANEOUS INTERFACE
The Miscellaneous Interface consist of a reset signal user definable sense signals and user definable enable signals
Pin
71
40
42
41
43
I O
O
O
I
I
I
Reset An active low TTL input signal which clears all registers The signal must be kept asserted for a
minimum amount of time Once the E RST signal is asserted the PLAYER
the specified amount of time to reset internal logic Note that bit zero of the Mode Register will be set to
zero (i e Stop Mode) See section 4 2 Stop Mode of Operation for more information
User Definable Sense Pin 0 A TTL input signal from a user defined source Sense Bit 0 (SB0) of the
User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once
the asserted signal is latched Sense Bit 0 can only be cleared through the Control Bus Interface even if
the signal is deasserted This ensures that the Control Bus Interface will record the source of events
which can cause interrupts
User Definable Sense Pin 1 A TTL input signal from a user defined source Sense Bit 1 (SB1) of the
User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once
the asserted signal is latched Sense Bit 1 can only be cleared through the Control Bus Interface even if
the signal is deasserted This ensures that the Control Bus Interface will record the source of events
which can cause interrupts
User Definable Enable Pin 0 A TTL output signal allowing control of external logic through the Control
Bus Interface EP0 is asserted deasserted through Enable Bit 0 (EB0) of the User Definable Register
(UDR) When Enable Bit 0 is set to zero EP0 is deasserted When Enable Bit 0 is set to one EP0 is
asserted
User Definable Enable Pin 1 A TTL output signal allowing control of external logic through the Control
Bus Interface EP1 is asserted deasserted through Enable Bit 1 (EB1) of the User Definable Register
(UDR) When Enable Bit 1 is set to zero EP1 is deasserted When Enable Bit 1 is set to one EP1 is
asserted
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93
Description
a
device should be allowed