DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 45
DP83256VF-AP
Manufacturer Part Number
DP83256VF-AP
Description
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83256VF-AP.pdf
(144 pages)
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Bit
D0
D1
D2
5 0 Registers
5 3 INTERRUPT CONDITION REGISTER (ICR)
The Interrupt Condition Register records the occurrence of an internal error event the detection of Line State an unsuccessful
write by the Control Bus Interface the expiration of an internal counter or the assertion of one or more of the User Definable
Sense pins
The Interrupt Condition Register will assert the Interrupt pin ( E INT) when one or more bits within the register are set to 1 and
the corresponding mask bits in the Interrupt Condition Mask Register (ICMR) are also set to 1
ACCESS RULES
Symbol
DPE
CPE
CCR
UDI
ADDRESS
D7
02h
PHY REQUEST DATA PARITY ERROR This bit will be set to 1 when
1 The PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register (CTSR) is set to 1 and
2 The Transmitter Block detects a parity error in the incoming PHY Request Data
The source of the data can be from the PHY Invalid Bus the Receive Bus the A Bus or the B Bus of the
Configuration Switch
Note Parity is only checked on data that goes into the transmitter block This means that any data that is just routed through the configuration
Control Bus DATA PARITY ERROR This bit will be set to 1 when the Control Bus Interface detects a parity error
in the incoming Control Bus Data (CBD
Control Bus WRITE COMMAND REJECT This bit will be set to 1 when an attempt to write into one of the
following read-only registers is made
Current Receive State Register (Register 08 CRSR)
Current Noise Count Register (Register 0F CNCR)
Current Noise Prescale Count Register (Register 10 CNPCR)
Current State Count Register (Register 13 CSCR)
Current State Prescale Count Register (Register 14 CSPCR)
Current Link Error Count Register (Register 16 CLECR)
Device ID Register (Register 18 IDR)
Current Injection Count Register (Register 19 CIJCR)
Scrub Timer Value Register (Register 25 STVR)
RCB
D6
switch without going into the transmit block is not checked
(Continued)
Always
READ
RCA
D5
Conditional
LEMT
WRITE
D4
k
7 0
CWI
l
D3
) CBP during a write cycle
45
Description
CCR
D2
CPE
D1
DPE
D0
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