MC68HC11E1 MOTOROLA [Motorola, Inc], MC68HC11E1 Datasheet - Page 36

• Manufacturer Part Number: MC68HC11E1
• Description: M68HC11E Series Programming Reference Guide
• Manufacturer: MOTOROLA [Motorola, Inc]

M68HC11ERG/AD
RAM and Register Mapping (INIT)
36
NOTE:
When IRV function is used, care must be taken to ensure that bus conflicts do
not occur. Data can be driven onto the bus even though the R/W line indicates
a high-impedance state on data bus pins.
PSEL[3:0] — Priority Select
RAM[3:0] — Internal RAM Map Position
Address:
Reset:
M68HC11E Series Programming Reference Guide
Can be written only while bit I in the CCR is set (interrupts disabled). These
bits select one interrupt source to be elevated above all other I bit related
sources. Refer to the following table.
Determine the upper four bits of RAM address. At reset, RAM is mapped to
$0000.
Read:
Write:
PSEL3
RAM[3:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0000
0001
0010
0011
0100
0101
0110
0111
$103D
RAM3
Bit 7
0
PSEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RAM2
6
0
PSEL1
$0000–$0xFF
$1000–$1xFF
$2000–$2xFF
$3000–$3xFF
$4000–$4xFF
$5000–$5xFF
$6000–$6xFF
$7000–$7xFF
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Address
RAM1
5
0
PSEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RAM0
4
0
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
SCI serial system
Reserved (default to IRQ)
IRQ (external pin or parallel I/O)
Real-time interrupt
Timer input capture 1
Timer input capture 2
Timer input capture 3
Timer output compare 1
Timer output compare 2
Timer output compare 3
Timer output compare 4
Timer input capture 4/output compare 5
Interrupt Source Promoted
REG3
RAM[3:0]
3
0
1010
1011
1110
1000
1001
1100
1101
1111
REG2
2
0
$C000–$CxFF
$D000–$DxFF
$A000–$AxFF
$B000–$BxFF
$E000–$ExFF
$8000–$8xFF
$9000–$9xFF
$F000–$FxFF
REG1
Address
1
0
MOTOROLA
REG0
Bit 0
1