MC68HC11E0CB2 MOTOROLA [Motorola, Inc], MC68HC11E0CB2 Datasheet - Page 108
MC68HC11E0CB2
Manufacturer Part Number
MC68HC11E0CB2
Description
8-channel, 8-bit analog-to-digital (A/D) converter
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC11E0CB2.pdf
(268 pages)
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Resets and Interrupts
Data Sheet
108
sequence results in which all I/O pins and functions are also restored to their initial
states.
To use the IRQ pin as a means of recovering from stop, the I bit in the CCR must
be clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from
stop regardless of the state of the X bit in the CCR, although the recovery sequence
depends on the state of the X bit. If X is set to 0 (XIRQ not masked), the MCU starts
up, beginning with the stacking sequence leading to normal service of the XIRQ
request. If X is set to 1 (XIRQ masked or inhibited), then processing continues with
the instruction that immediately follows the STOP instruction, and no XIRQ
interrupt service is requested or pending.
Because the oscillator is stopped in stop mode, a restart delay may be imposed to
allow oscillator stabilization upon leaving stop. If the internal oscillator is being
used, this delay is required; however, if a stable external oscillator is being used,
the DLY control bit can be used to bypass this startup delay. The DLY control bit is
set by reset and can be optionally cleared during initialization. If the DLY equal to
0 option is used to avoid startup delay on recovery from stop, then reset should not
be used as the means of recovering from stop, as this causes DLY to be set again
by reset, imposing the restart delay. This same delay also applies to power-on
reset, regardless of the state of the DLY control bit, but does not apply to a reset
while the clocks are running.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Resets and Interrupts
M68HC11E Family — Rev. 5
MOTOROLA
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