PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 387

• Manufacturer Part Number: PIC18F2423
• Description: 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

© 2007 Microchip Technology Inc.
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 351
Example SPI Master Mode (CKE = 1) ..................... 352
Example SPI Slave Mode (CKE = 0) ....................... 353
Example SPI Slave Mode (CKE = 1) ....................... 354
External Clock (All Modes Except PLL) ................... 344
Fail-Safe Clock Monitor (FSCM) .............................. 266
First Start Bit Timing ................................................ 193
Full-Bridge PWM Output .......................................... 153
Half-Bridge PWM Output ......................................... 152
High/Low-Voltage Detect Characteristics ................ 341
High-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4423/4523) ................... 350
Parallel Slave Port (PSP) Read ............................... 121
Parallel Slave Port (PSP) Write ............................... 121
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 155
PWM Direction Change at Near
PWM Output ............................................................ 144
Repeat Start Condition ............................................. 194
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................ 220
Slave Synchronization ............................................. 167
Slow V
SPI Mode (Master Mode) ......................................... 166
SPI Mode (Slave Mode, CKE = 0) ........................... 168
SPI Mode (Slave Mode, CKE = 1) ........................... 168
Synchronous Reception
Synchronous Transmission ...................................... 221
Synchronous Transmission
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 355
C Bus Start/Stop Bits ............................................. 355
C Master Mode (7 or 10-Bit Transmission) ........... 196
C Master Mode (7-Bit Reception) .......................... 197
C Slave Mode (10-Bit Reception, SEN = 0) .......... 182
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 1) .......... 187
C Slave Mode (10-Bit Transmission) ..................... 183
C Slave Mode (7-bit Reception, SEN = 0) ............. 178
C Slave Mode (7-bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 1) ............ 186
C Slave Mode (7-Bit Transmission) ....................... 180
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 198
(Master/Slave) ................................................. 359
(Master/Slave) ................................................. 359
(VDIRMAG = 1) ................................................ 250
ADMSK = 01001) ............................................. 181
ADMSK = 01011) ............................................. 179
Sequence (7 or 10-Bit Address Mode) ............ 188
(VDIRMAG = 0) ................................................ 249
Auto-Restart Disabled) .................................... 158
Auto-Restart Enabled) ..................................... 158
100% Duty Cycle ............................................. 155
Start-up Timer (OST), Power-up
Timer (PWRT) .................................................. 347
V
(Master Mode, SREN) ..................................... 223
(Through TXEN) .............................................. 222
DD
DD
Rise > T
Rise Time (MCLR Tied to V
2
2
C Bus Data ........................................ 357
C Bus Start/Stop Bits ........................ 357
PWRT
) ............................................ 47
DD
,
PIC18F2423/2523/4423/4523
Preliminary
Timing Diagrams and Specifications ............................... 344
Top-of-Stack Access .......................................................... 54
TRISE Register
TSTFSZ ........................................................................... 311
Two-Speed Start-up ................................................. 253, 264
Two-Word Instructions
TXSTA Register
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 348
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake from Idle to
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 36
A/D Conversion Requirements ................................ 361
Capture/Compare/PWM Requirements ................... 349
CLKO and I/O Requirements ................................... 346
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 344
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 345
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
PSPMODE Bit ......................................................... 114
Example Cases ......................................................... 58
BRGH Bit ................................................................. 209
2
2
C Bus Data Requirements
C Bus Start/Stop Bits Requirements
(MCLR Tied to V
(MCLR Rises After T
(MCLR Rises Before T
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 264
Run Mode .......................................................... 38
PRI_RUN Mode ................................................. 36
PRI_RUN Mode (HSPLL) .................................. 35
Requirements .................................................. 359
Requirements .................................................. 359
(Master Mode, CKE = 0) .................................. 351
(Master Mode, CKE = 1) .................................. 352
(Slave Mode, CKE = 0) .................................... 353
(Slave Mode, CKE = 1) .................................... 354
(Slave Mode) ................................................... 356
(Slave Mode) ................................................... 355
Requirements .................................................. 358
Requirements .................................................. 357
(PIC18F4423/4523) ......................................... 350
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 347
Clock Requirements ........................................ 348
2
2
C Bus Data
C Bus Start/Stop Bits
DD
DD
) .......................................... 47
, V
OST
DD
OST
Completes) ................ 46
Rise < T
Completes) ............. 46
DS39755B-page 385
PWRT
) ........... 46