PIC18F2510 MICROCHIP [Microchip Technology], PIC18F2510 Datasheet - Page 37

• Manufacturer Part Number: PIC18F2510
• Description: 28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 3-1:
FIGURE 3-2:
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no
distinguishable differences between PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
 2004 Microchip Technology Inc.
Note 1: Clock transition typically occurs within 2-4 T
Peripheral
Program
Counter
T1OSI
Note 1: T
OSC1
Clock
Clock
CPU Clock
RC_RUN MODE
CPU
Peripheral
PLL Clock
Program
Counter
Output
T1OSI
OSC1
Clock
2: Clock transition typically occurs within 2-4 T
Q1
SCS1:SCS0 bits changed
OST
Q2
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
PC
= 1024 T
Q3
Q4
Q1
OSC
Q1
; T
1
T
OST
PLL
PC
(1)
= 2 ms (approx). These intervals are not shown to scale.
2
Q2
Clock Transition
OSTS bit set
3
T
Q3
PLL (1)
OSC
PC + 2
(1)
Q4
n-1
.
OSC
.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
n
Q1
1
Note:
Transition
2
Clock
PIC18F2X1X/4X1X
n-1 n
(2)
Q2
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
PC + 2
DD
Q3
/F
Q2
OSC
Q4
Q3 Q4
specifications are violated.
Q1
Q1
DD
PC + 4
Q2
is less than 3V, it is
Q2
PC + 4
DS39636A-page 35
Q3
Q3
DD
.