MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 136

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

DMA
DMA Status and
Control Register
MC68HC708XL36
136
NOTE:
Address: $004D
The DMA status and control register:
DMAP — DMA Priority Bit
When DMAP = 0, a CPU interrupt clears the TECx bit if the channel has
a pending DMA transfer. Software must re-enable channel x after each
CPU interrupt by setting the TECx bit.
Reset:
Read:
Write:
•
•
•
This read/write bit controls the priority of CPU interrupt requests
during DMA transfers. Reset clears the DMAP bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = CPU interrupt requests inhibited during DMA transfers — When
0 = CPU interrupt requests recognized during DMA transfers —
Flags completion of DMA transfers.
Controls looping of source and destination address counts.
Controls priority of DMA service requests and CPU interrupt
requests.
Figure 18. DMA Status and Control Register (DSC)
DMAP
Bit 7
DMAP is set, a CPU interrupt request is not recognized until
the end of the current DMA transfer. During a block transfer,
the increase in CPU interrupt latency depends on the block
size and on the bus bandwidth bits, BB[1:0]. (See
Control Register 1
When DMAP is clear, a CPU interrupt request is recognized
after the transfer of the current byte or word in the current DMA
transfer. The CPU interrupt disables the DMA by clearing the
transfer enable bits, TEC[2:0]. (See
on page 133.) The DMA can increase CPU interrupt latency by
up to three cycles in a byte transfer or five cycles in a word
transfer.
0
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L2
6
0
DMA
L1
5
0
on page 133.)
L0
4
0
DMAWE
3
0
DMA Control Register 1
IFC2
2
0
IFC1
1
0
DMA
MOTOROLA
26-dma_b
IFC0
Bit 0
0