MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 194

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

TIM
TIM Channel 3
Status and Control
Register
MC68HC708XL36
194
NOTE:
Address:
CHxF— Channel x Flag Bit
Reading the high byte of the timer channel x registers (TCHxH) inhibits
the CHxF bit until the low byte (TCHxL) is read.
Reset:
Read:
Write:
Figure 11. TIM Channel 3 Status and Control Register (TSC3)
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled
(CHxIE:DMAxS = 1:0), clear CHxF by reading TIM channel x status
and control register with CHxF set and then writing a logic 0 to CHxF.
If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
When TIM DMA service requests are enabled (CHxIE:DMAxS = 1:1),
clear CHxF by reading or writing to the low byte of the TIM channel x
registers (TCHxL).
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
$002F
CH3F
Bit 7
0
0
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= Unimplemented
CH3IE
6
0
TIM
5
0
0
MS3A
4
0
ELS3B
3
0
ELS3A
2
0
TOV3
1
0
MOTOROLA
CH3MAX
24-tim4_b
Bit 0
0