MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 260

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

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2. DMA latency should be short enough so that an SCRF is serviced
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before the next SCRF occurs. If DMA latency is long enough for a
new SCRF to occur before servicing an error bit, then:
a. Overruns occur. Set the ORIE bit to enable SCI error CPU
b. If the CPU does not service an overrun interrupt request, the
Then the DMA could read the SCI data register, the second
step in clearing it, thereby clearing all error bits. The next read
of the data register would miss any error bits that were set.
interrupt requests and service the overrun in an interrupt
routine. In a message-based system, disable the DMA in the
interrupt routine and manually recover. Otherwise, the byte
that was lost in the overrun could prevent the DMA from
reaching its byte count. If the DMA reaches it byte count in the
following message, two messages may be corrupted.
DMA can eventually clear the SCRF bit by reading the SCI
data register. The OR bit remains set. Each time a new byte
sets the SCRF bit, new data transfers from the shift register to
the SCI data register (provided that another overrun does not
occur), even though the OR bit is set. The DMA removed the
overrun condition by reading the data register, but the OR bit
has not been cleared.
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