MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 90

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

CGM
Acquisition and
Tracking Modes
Manual and
Automatic PLL
Bandwidth Modes
MC68HC708XL36
90
The PLL filter is manually or automatically configurable into one of two
operating modes:
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See
100.) If PLL CPU interrupt requests are enabled, the software can wait
for a PLL CPU interrupt request and then check the LOCK bit. If CPU
interrupts are disabled, software can poll the LOCK bit continuously
(during PLL startup, usually) or at periodic intervals. In either case, when
the LOCK bit is set, the VCO clock is safe to use as the source for the
base clock. (See
is selected as the source for the base clock and the LOCK bit is clear,
the PLL has suffered a severe noise hit and the software must take
appropriate action, depending on the application. (See
page 104.)
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Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth
control register. (See
on page 100.)
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See
is automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
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PLL Bandwidth Control Register (PBWC)
Base Clock Selector Circuit
Base Clock Selector Circuit
CGM
PLL Bandwidth Control Register (PBWC)
on page 94.) If the VCO
on page 94.) The PLL
Interrupts
MOTOROLA
on page
8-cgm1m_a
on