LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 122

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
6.7
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
nCS, nRD
Data Bus
A[7:1]
Note: The “Data Bus” width is 16 bits
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
In this mode the upper address inputs are not decoded, and any write to the LAN9115 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9115. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
TX Data FIFO Direct PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
DATASHEET
122
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
165
32
13
0
7
0
0
TYP
MAX
SMSC LAN9115
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns