LAN9215-MT-E2 SMSC [SMSC Corporation], LAN9215-MT-E2 Datasheet - Page 108

• Manufacturer Part Number: LAN9215-MT-E2
• Description: Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.5 (07-18-06)
5.5
(IN DECIMAL)
INDEX
17
18
27
29
30
31
0
1
2
3
4
5
6
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC
via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers.
PHY Register Indexes are shown in
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of
PHY Registers
the PHY Basic Control Register (Reset) is set.
Table 5.8 LAN9215 PHY Control and Status Register
REGISTER NAME
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes Register
Special Control/Status Indications
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
PHY CONTROL AND STATUS REGISTERS
DATASHEET
Table 5.8, "LAN9215 PHY Control and Status
108
Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Register".
SMSC LAN9215
Datasheet