PIC18F25J11-I/PT MICROCHIP [Microchip Technology], PIC18F25J11-I/PT Datasheet - Page 53
PIC18F25J11-I/PT
Manufacturer Part Number
PIC18F25J11-I/PT
Description
28/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J11-IPT.pdf
(528 pages)
- Current page: 53 of 528
- Download datasheet (9Mb)
REGISTER 3-3:
REGISTER 3-4:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
All register bits are maintained unless: V
Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
All register bits are maintained unless: V
Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1
(BANKED F4Fh)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
Deep Sleep Persistent General Purpose bits
Deep Sleep Persistent General Purpose bits
DDCORE
DDCORE
R/W-xxxx
R/W-xxxx
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
drops below the normal BOR threshold outside of Deep
drops below the normal BOR threshold outside of Deep
PIC18F46J11 FAMILY
(1)
(1)
DD
DD
is hard cycled to near V
is hard cycled to near V
x = Bit is unknown
x = Bit is unknown
DD
DD
drops below the
drops below the
SS
SS
DS39932C-page 53
.
.
bit 0
bit 0
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