PEB2096 SIEMENS [Siemens Semiconductor Group], PEB2096 Datasheet - Page 19

• Manufacturer Part Number: PEB2096
• Description: Octal Transceiver for UPN Interfaces OCTAT-P
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

according to their numbers, i.e. LI0a,b is allocated to IOM channel 0, LI1 to channel 1,
and so on.
For details refer to figures 14 and 15 and to the chapter 5.8 and the IOM Interface
Specification, Rev. 2.
Monitor Channel
The monitor channel is used to convey messages (e.g. when a bit error occurs on U
or for access to internal registers: Identification Register, General Configuration
Register, Bit Error Register, Configuration Register for U
The PEB 2096, OCTAT-P, has implemented the monitor channel protocol according to
the IOM Interface Specification, Rev. 2, in the first of the eight IOM channels allocated
to the eight U
C/I-Channel
The C/I-channel is used for communication between the PEB 2096, OCTAT-P, and a
processor via a layer-2 device, to control and monitor layer-1 functions. The OCTAT-P
has 8 IOM-2 channels and thus 8 C/I-channels; one for each transceiver.
The codes originating from layer-2 devices are called “commands”, those from the
PEB 2096, OCTAT-P, are called “indications”. For a list of the C/I (command/indication)
codes and their use, refer to the chapters 3.8.
2.2.3
The OCTAT-P provides fully IEEE Standard 1149.1 compatible boundary scan support
to allow cost effective board testing. It consists of:
• Complete boundary scan test
• Test access port controller (TAP)
• Four dedicated pins (TCK, TMS, TDI, TDO)
• One 32-bit IDCODE register
• Specific functions for LIna,b
In order to allow the use of the eight channels also with a maximum clock rate of
2,048 kHz provided by the system, the OCTAT-P can also run the IOM interface with
only half the nominal DCL clock rate, i.e. 2,048 kHz for 2,048 kbit/s (Input pin IDS = 1).
The OCTAT-P requires three IOM frames to synchronize to the DCL frequency. A
corrupted IOM frame caused by different amount of DCL pulses within two consecutive
IOM frames (e.g. caused by spikes on DCL or FSC) resets internally all registers and the
activation and deactivation state machine, figure 21.
The allocation between U
Semiconductor Group
JTAG Boundary Scan Test Interface
PN
interfaces. Refer also to the chapter 3.7.
PN
line interfaces and the IOM-2 interface channels is
19
PN
and Test Registers.
PEB 2096
01.96
PN
)