LAN9311i SMSC [SMSC Corporation], LAN9311i Datasheet - Page 448

• Manufacturer Part Number: LAN9311i
• Description: Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.6 (08-18-09)
15.5.5
A[x:5], END_SEL
SYMBOL
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
nCS, nRD
D[15:0]
A[4:1]
PIO Burst Read Cycle Timing
Please refer to
Note: A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends
Note: A[1] must toggle, fresh data is supplied each time A[1] toggles.
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD Valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
when either or both nCS and nRD are de-asserted. These signals may be asserted and de-
asserted in any order.
t
asu
Section 8.5.5, "PIO Burst Reads," on page 108
Table 15.9 PIO Burst Read Cycle Timing Values
t
don
Figure 15.5 PIO Burst Read Cycle Timing
DESCRIPTION
t
acyc
t
csdv
DATASHEET
t
adv
t
acyc
448
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
t
adv
for a functional description of this mode.
MIN
13
45
0
0
0
0
t
adv
t
acyc
t
TYP
ah
SMSC LAN9311/LAN9311i
t
doh
t
MAX
doff
t
csh
30
40
9
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS