PEB2447 SIEMENS [Siemens Semiconductor Group], PEB2447 Datasheet - Page 41

• Manufacturer Part Number: PEB2447
• Description: Memory Time Switch Extended Large MTSXL
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4.13
Access in demultiplexed P-interface mode:
Read/write, address:
Reset value:
ADSR
ICS4..0
RRE
These 16 registers determine the individual clock shift of inputs IN0 to IN15.
If more than sixteen inputs are used, two inputs are controlled by one ICSR register:
ICSR0
ICSR1
ICSR2
.
.
ICSR7
ICSR8
ICSR9
ICSR10
.
.
ICSR15
The values of ICSR (15:0) can be adjusted without producing bit errors:
– clockrate = 2
– clockrate = 4
Semiconductor Group
possible adjustment is one half clock period forward or backward.
possible adjustment is one clock period backward or two clock periods forward.
Input Clock Shift Register Bank ICSR (15:0)
ADRS
Bit 7
datarate
datarate
controls
”
”
”
”
”
”
”
Add Shift Register; a three bit shift register is inserted into the
corresponding input(s), resulting in an additional offset for that/those
input(s). The sampling point is shifted “backwards” by 3 clock cycles
(see figure 9).
Note: ADSR has to be set to “0” in modes 1 and 3.
Input Clock Shift; the value of ICS4..0 determines the number of
clock cycles by which the bit sampling point is shifted forward in all
input modes according to figure 9.
Receive on Rising Edge; the PCM data of the corresponding
input(s) is sampled with the rising edge of the clock, if this bit is set.
0
ICS4
10
00
H
H
ICS3
... 1F
IN0, IN8
IN1, IN9
IN2, IN10
.
.
IN7, IN15
IN16, IN24
IN17, IN25
IN18, IN16
.
.
IN23, IN31
H
41
ICS2
ICS1
Detailed Register Description
ICS0
RRE
Bit 0
PEB 2447
03.97