SAB80C515A-5 SIEMENS [Siemens Semiconductor Group], SAB80C515A-5 Datasheet
SAB80C515A-5
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SAB80C515A-5 Summary of contents
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Microcomputer Components SAB 80C515A/83C515A-5 8-Bit CMOS Single-Chip Microcontroller Family Addendum to User's Manual SAB 80515/80C515 08.95 ...
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SAB 80C515A/83C515A-5 Addendum Revision History: Previous Version: Page Subjects (major changes since last revision) 3-6 CCH4 / CCL4 deleted 3-16 Table supplemented (MOVX @Ri 00) 5-4 Falling edge for P4.0 / ADST in figure 5-2 added 5-10 ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction The SAB 80C515A is a superset of the high end microcontroller SAB 80C515. While maintaining all architectural and operational characteristics of the SAB 80C515 the SAB 80C515A incorporates more on-chip RAM. A new 10-bit A/D-Converter is implemented as ...
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The SAB 80C515A is available in two different versions: – "ROMless" Version SAB 80C515A. Although this part is called "ROMless" there is an internal ROM of 2 KByte (for Test and Loader Software) – ROM Version SAB 83C515A-5. This part ...
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Fundamental Structure The SAB 80C515A/83C515A high-end member of the Siemens SAB 8051 microcontroller family designed in Siemens ACMOS technology and based on the SAB 8051 architecture. ACMOS is a technology which combines high-speed and density ...
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Figure 2-1 Block Diagram of the SAB 80C515A / 83C515A-5 Semiconductor Group Fundamental Structure 2-2 ...
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Memory Organization According to the SAB 8051 architecture, the SAB 80C515A has separate address spaces for program and data memory. Figure 3-1 illustrates the mapping of address spaces. Figure 3-1 Memory Map Semiconductor Group Memory Organization 3-1 ...
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Program Memory, ROM Protection The SAB 83C515A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C515A has no internal ROM. The program memory can externally be expanded Kbyte. Pin EA determines whether program fetches below ...
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Data Memory The data memory space consists of an internal and an external memory space. The SAB 80C515A contains another 1 kByte of On-Chip RAM additional to the 256 Bytes internal RAM of the base type SAB 80C515. This ...
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Table 3-1 Special Function Register Address Register DPL 83 H DPH 84 H (WDTL (WDTH WDTREL 87 H PCON 88 H TCON TMOD 8A ...
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Table 3-1, Special Function Register (cont’d) Address Register C0 H IRCON CCEN C2 H CCL1 C3 H CCH1 C4 H CCL2 C5 H CCH2 C6 H CCL3 C7 H CCH3 C8 H T2CON reserved ...
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Table 3-2 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte PSW Program Status Word Register SP Stack Pointer A/D- ADCON0 A/D Converter Control Register ...
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Table 3-2, Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Ports P0 Port 0 P1 Port 1 P2 Port 2 P3 Port 3 P4 Port 4 P5 Port 5 P6 Port 6, Analog/Digital Input Power Save PCON Power ...
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Architecture of the XRAM The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the contents is undefined, while it remains unchanged during and after a reset or HW Power Down if ...
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Accesses to XRAM using the Registers R0/R1 The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX ...
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Figure 3-2 Write Page Address to Port 2 MOV P2, pageaddress will write the page address to Port 2 and XPAGE-Register. When external RAM accessed in the XRAM address range (F800 H - FFFF H ) XRAM ...
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Figure 3-3 Write Page Address to XPAGE The page address is only written to XPAGE-register. Port 2 is available for addresses or I/O-Data. See figure 3-4 to see what happens when Port 2 is used as I/O-Port. Semiconductor Group Memory ...
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Figure 3-4 Use of Port 2 as I/O-Port At a write to Port 2, XRAM address in XPAGE-register will be overwritten because of the concurrent write to Port 2 and XPAGE-register. So whenever XRAM is used and the XRAM address ...
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The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed from XPAGE and Ri is less than the XRAM address range, then an external access is performed. For the SAB ...
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Control of XRAM in the SAB 80C515A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On-Chip RAM in XDATA range ( XRAM). Special Function Register SYSCON ...
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A hardware protection is done by an unsymmetric latch at XMAP0-bit. A unintentional disabling of XRAM could be dangerous since indeterminate values could be read from external bus. To avoid this the XMAP-bit is forced to ’1’ only by reset. ...
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Semiconductor Group Memory Organization 3-16 ...
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System Reset 4.1 Additional Hardware Power Down Mode in the SAB 80C515A The SAB 80C515A has an additional Power Down Mode which can be initiated by an external signal at a dedicated pin. This pin is labeled HWPD and ...
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Table 4-1 Status of all Pins During Hardware Power Down Mode Pins Status P0, P1, P2, P3, P4, P5, Floating outputs/ P6 Disabled input function EA Active input PE/SWD Active input, Pull-up resistor Disabled during HW power down XTAL 1 ...
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The power down state is maintained while pin HWPD is held active. If HWPD goes to high level (inactive state) an automatic start up procedure is performed: – First the pins leave their floating condition and enter their default reset ...
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Hardware Power Down Reset Timing Following figures are showing the timing diagrams for entering (figure 4-1) and leaving (figure 4-2) the Hardware Power Down Mode. If there is only a short signal at pin HWPD (i.e. HWPD is sampled ...
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Figure 4-1 Timing Diagram of Entering Hardware Power Down Mode Semiconductor Group 4-5 System Reset ...
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Figure 4-2 Timing Diagram of Leaving Hardware Power Down Mode Semiconductor Group 4-6 System Reset ...
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Figure 4-3 Timing Diagram of Hardware Power Down Mode, HWPD-Pin is active for only one Cycle Semiconductor Group 4-7 System Reset ...
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Fast Internal Reset after Power-On The SAB 80C515A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 4-4 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the ...
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After the on-chip oscillator finally has started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of 768 cycles of the RC oscillator in order to allow the oscillation of ...
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Figure 4-4 Power-on of the SAB 80C515A Semiconductor Group 4-10 System Reset ...
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On-Chip Peripheral Components Digital I/O Port Circuitry To realize the Hardware Power Down Mode with floating Port pins in the SAB 80C515A/83C515A-5 the standard port structure used in the 8051 Family is modified (figure 5-1). The FETs p4, p5 ...
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P1 and p3 are not active during Hardware Power Down activated only for two oscillator periods if a 0-to-1 transition is programmed to the port pin (not possible during HWPD turned off during reset state (also ...
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A/D-Converter In the SAB 80C515A a new high performance/high speed 8-channel 10-bit A/D-Converter is implemented. Its successive approximation technique provides 7 s conversion time ( MHz). The conversion principle is upward compatible to the one ...
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Figure 5-2 10-Bit A/D-Converter Semiconductor Group On-Chip Peripheral Components 5-4 ...
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Special Function Registers ADCON0, ADCON1 MSB Bit No Addr. BD CLK 0D8 H MSB Bit No Addr. ADCL 0DC H These bits are not used in controling A/D converter functions in the 80C515A Bit Function ADEX ...
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Special Function Register ADDATH, ADDATL MSB Bit No Addr. msb 0D9 H MSB Bit No Addr. lbs 0DA H These bits are not used for conversion result The reset value of ADDAT H and ADDATL is ...
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A/D Converter Timing After a conversion has been started (by a write to ADDATL, external start by P4.0/ADST or in continuous mode) the analog input voltage is sampled for 4 clock cycles. The analog source must be capable of charging ...
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New Baud Rate Generator for Serial Channel The Serial Channel has a new baud rate generator which provides greater flexibility and better resolution. It substitutes the 80C515’s baud rate generator at the Serial Channel which provides only 4.8 kBaud ...
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Special Function Register S0RELH, S0RELL MSB Bit No Addr. 0BA H MSB Bit No Addr. 0AA H shaded areas are not used for programming the baudrate timer Bit SRELH.0-1 SRELL.0-7 Reset value of SRELL is 0D9 ...
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Figure 5-5 shows a block diagram of the options available for baud rate generation of Serial Channel fully compatible superset of the functionality of the SAB 80C515. The new baud rate generator can be used in modes ...
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Fail Save Mechanisms The SAB 80C515A offers two on-chip peripherals which ensure an automatic ’fail-save’ reaction in cases where the controller’s hardware fails or the software hangs up: – Programmable Watchdog Timer (WDT) with variable time-out period from 512 ...
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Programmable Watchdog Timer To protect the system against software upset, the user’s program has to clear the watchdog within a previously programmed time period. If the software fails to do this periodical refresh of the Watchdog Timer, an internal ...
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Special Function Register WDTREL (Address 086 H ) Bit No. MSB 7 6 086 H Bit Function WDTREL.7 Prescaler select bit. When set, the watchdog timer is clocked through an additional divide-by-16 prescaler (see figure 12). WDTREL.6 Seven bit reload ...
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Starting the Watchdog Timer There are two ways to start the Watchdog Timer depending on the level applied to the pin PE/SWD (Power Down Modes enable # / Start Watchdog Timer; pin 4). This pin serves two functions (new for ...
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Refreshing the Watchdog Timer At the same time the Watchdog Timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. Once started the Watchdog Timer cannot be stopped by software but can be refreshed ...
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Figure 5-7 Watchdog Status Flags and Reset Requests Special Function Register IP0 (Address 0A9 H ) Bit No. MSB 7 6 086 H OWDS WDTS These bits are not used for Watchdog Timer Bit Function WDTS Watchdog timer status flag. ...
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Oscillator Watchdog Unit The unit serves three functions: – Monitoring of the on-chip oscillator’s function. The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the ...
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Detailed Description of the Oscillator Watchdog Unit Figure 5-8 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on- chip ...
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The frequency coming from the RC oscillator is divided by 5 and compared to the on-chip oscillator’s frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects ...
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High-Performance 8-Bit CMOS Single-Chip Microcontroller Preliminary SAB 83C515A-5 SAB 80C515A SAB 80C515A / 83C515A- MHz operation frequency ROM (SAB 83C515A-5 only, ROM-Protection available) 256 8 on-chip RAM Additional on-chip RAM (XRAM) ...
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Ordering Information Type Ordering Code SAB 80C515A-N18 Q67120-C0581 SAB 83C515A-5N18 Q67120-DXXXX P-LCC-68 SAB 80C515A-N18-T3 Q67120-C0784 SAB 83C515A-5N18-T3 Q67120-DXXXX P-LCC-68 SAB 80C515A-M18-T3 Q67120-C0851 SAB 83C515A-5M18-T3 Q67120-DXXXX P-MQFP-80 with mask-programmable ROM, Notes : Versions for extended temperature range The ordering number of ...
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Logic Symbol Semiconductor Group SAB 80C515A/83C515A-5 6-3 ...
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The pin functions of the SAB 80C515A are identical with those of the SAB 80C515 with following exception: Pin Pin Configuration (P-LCC-68) Semiconductor Group SAB 80C515A HWPD P0.4/ADST PE/SWD 6-4 SAB 80C515A/83C515A-5 SAB 80C515 V CC P4.0 ...
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RESET 1 N.C. VAREF VAGND P6.7 / AIN7 5 P6.6 / AIN6 P6.5 / AIN5 P6.4 / AIN4 P6.3 / AIN3 P6.2 / AIN2 10 P6.1 / AIN1 P6.0 / AIN0 N.C. N.C. P3.0 / RXD0 15 P3.1 / ...
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Pin Definitions and Functions Symbol Pin Pin P-LCC-68 P-MQFP-80 P4.0-P4.7 1-3, 5-9 72-74, 76-80 PE/SWD 4 75 RESET AREF1 AGND Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) I/O Port 4 ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP-80 P6.7-P6.0 13-20 5-12 P3.0-P3.7 21-28 15-22 Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) I Port 8-bit unidirectional input port to the A/ D converter. Port ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP-80 P1.7 - 29-36 24-31 P1.0 XTAL2 39 36 Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) I/O Port 8-bit bidirectional I/O port with internal pullup resistors. ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP-80 XTAL1 40 37 P2.0-P2.7 41-48 38-45 PSEN 49 47 ALE 50 48 Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) XTAL1 - Output of the inverting oscillator amplifier. To ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP- P0.0-P0.7 52-59 52-59 P5.7-P5.0 60-67 60-67 HWPD 32 34 N.C. – 2, 13, 14, 23, 46, 50, ...
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Figure 1 Block Diagram Semiconductor Group SAB 80C515A/83C515A-5 6-11 ...
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Functional Description The SAB 80C515A is based on 8051 architecture fully compatible member of the Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced SAB 80C515. The SAB 80C515A is therefore code compatible with the SAB 80C515. ...
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Program Memory ('Code Space') The SAB 83C515A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C515A has no internal ROM. The program memory can externally be expanded Kbyte. Pin EA determines whether program fetches below address ...
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Data Memory ('Data Space') The data memory space consists of an internal and an external memory space.The SAB 80C515A contains another 1 Kbyte on On-Chip RAM additional to the 256-bytes internal RAM of the base type SAB 80C515. This RAM ...
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Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. Note reset occurs during a write operation to XRAM, the effect ...
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Special Function Register XPAGE Addr The reset value of XPAGE is 00 XPAGE can be set and read by software. The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the ...
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Control of XRAM in the SAB 80C515A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On-Chip RAM (XRAM). Special Function Register SYSCON Addr. 0B1 H Bit Function ...
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XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM could be dangerous since indeterminate values would be read from external bus. To avoid this the XMAP-bit is forced to '1' only by reset. Additionally, during reset ...
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Semiconductor Group SAB 80C515A/83C515A-5 6-19 ...
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Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function registers include arithmetic registers, pointers, and registers that provide an interface between the CPU ...
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Table 2: Special Function Register (cont’d) Address Register SYSCON H B2 reserved H B3 reserved H B4 reserved H B5 reserved H B6 reserved H B7 reserved EN1 H B9 IP1 H ...
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Table 2: Special Function Register (cont’d) Address Register reserved F1 H reserved F2 H reserved F3 H reserved F4 H reserved F5 H reserved F6 H reserved Bit-addressable special function registers 2) X ...
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Table 3 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte PSW Program Status Word Register SP Stack Pointer A/D- ADCON0 A/D Converter Control Register ...
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Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Ports Pow.Sav.M PCON ode Serial ADCON0 2) Channels PCON 2) SBUF SCON SRELL SRELH Timer 0/ TCON Timer 1 TH0 TH1 TL0 ...
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A/D Converter In the SAB 80C515A a new high performance / high-speed 8-channel 10-bit A/D-Converter (ADC) is implemented. Its successive approximation technique provides 7 s conversion time ( MHz). The conversion principle is upward compatible to the one ...
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Figure 3 Block Diagram A/D Converter Semiconductor Group SAB 80C515A/83C515A-5 6-26 ...
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Timers /Counters The SAB 80C515A contains three 16-bit timers/counters wich are useful in many applications for timing and counting. the input clock for wach timer/counter is 1/12 of the oscillator frequency in the timer operation or can be taken from ...
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Capture This feature permits saving of the actual timer/counter contents into a selected register upon an external event or a software write operation. Two modes are provided to latch the current 16-bit value of timer 2 registers TL2 and TH2 ...
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Figure 4 Block Diagram of Timer/Counter 2 Semiconductor Group SAB 80C515A/83C515A-5 6-29 ...
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Interrupt Structure The SAB 80C515A has 12 interrupt vectors with the following vector addresses and request flags. Table 4 Interrupt Sources and Vectors Source (Request Flags) IE0 TF0 IE1 TF1 TF2 + EXF2 IADC IEX2 IEX3 IEX4 ...
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Figure 5 Interrupt Request Sources Semiconductor Group SAB 80C515A/83C515A-5 6-31 ...
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Figure 6 Interrupt Priority Level Structure Semiconductor Group SAB 80C515A/83C515A-5 6-32 ...
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I/O Ports The SAB 80C515A has six 8-bit I/O ports and one input port. Port open-drain bidirectional I/O port, while ports are quasi-bidirectional I/O ports with internal pull-up resistors. That means, when configured as ...
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Power Saving Modes The SAB 80C515A provides – due to Siemens ACMOS technology – four modes in which power consumption can be significantly reduced. – The Slow Down Mode The controller keeps up the full operating functionality, but is driven ...
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Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardware Power Down Mode. The control pin PE/SWD has no control function in this mode. It enables and disables only the use of software controlled power ...
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Software Power Down Mode The power down mode is entered by two consecutive instructions directly following each other. The first instruction has to set the flag PDE (power down enable) and must not set PDS (power down set). The following ...
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Table 5 Status of all pins during Idle Mode, Power Down Mode and Hardware Power Down Mode Pins Idle Mode Last instruction executed from internal external ROM P0 Data float P1 Data Dat alt outputs alt outputsa P2 Data Address ...
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Serial Interface The SAB 80C515A has a full duplex and receive buffered serial interface functionally identical with the serial interface of the SAB 8051. Table 6 shows possible configurations and the according baud rates. Table 6 Baud Rate ...
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The Serial Interface can operate in 4 modes: Mode 0: Shift register mode: Serial data enters and exits through R are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the oscillator fre- quency. Mode 1: 8-bit UART, ...
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Fail Safe Units The SAB 80C515A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: – a programmable watchdog timer (WDT), with variable time-out period from 512 appr. 1.1 s ...
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Figure 8 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the frequency comparator. Figure 7 Block Diagram of the Programmable Watchdog Timer Figure 8 Functional Block ...
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Fast internal reset after power-on The SAB 80C515A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally members of the 8051 family (like the SAB 80C515) enter their default reset state not before the ...
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Absolute Maximum Ratings Ambient temperature under bias Storage temperature Voltage on V pins with respect to ground (V CC Voltage on any pin with respect to ground (V Input current on any pin during overload condition Absolute sum of all ...
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DC Characteristics (cont’d) Parameter Output low voltage (ports Output low voltage (ports 0, ALE, RESET) Output high voltage, (ports1 Output high voltage (port 0 in external bus mode,- ALE, PSEN) Logic ...
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Notes for page 44: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V of ALE and ports and 5. The noise is due to external bus capacitance ...
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A/D Converter Characteristics = – AREF CC AGND Parameter Analog input capacitance C Sample time (inc. load time) Conversion time (inc. sample time) Total ...
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AC Characteristics = – for port 0, ALE and PSEN outputs = 100 pF Parameter Symbol Program Memory Characteristics ALE pulse width t Address setup to ALE ...
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AC Characteristics (cont’d) Parameter Symbol External Data Memory Characteristics RD pulse width t WR pulse width t Address hold after t ALE RD to valid data in t RLDV DATA hold after RD t Data float after RD t ALE ...
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Program Memory Read Cycle Data Memory Read Cycle Semiconductor Group SAB 80C515A/83C515A-5 6-49 ...
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Data Memory Write Cycle Semiconductor Group SAB 80C515A/83C515A-5 6-50 ...
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AC Characteristics (cont'd) Parameter Symbol External Clock Drive Oscillator period t CLCL High time t CHCX Low time t CLCX Rise time t CLCH Fall time t CHCL Oscillator frequency 1/t External Clock Cycle Semiconductor Group Limit values Variable clock ...
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AC Characteristics (cont’d) Parameter Symbol System Clock Timing ALE to CLKOUT t LLSH CLKOUT high time t SHSL CLKOUT low time t SLSH CLKOUT low to ALE t SLLH high System Clock Timing Semiconductor Group SAB 80C515A/83C515A-5 Limit values 18 ...
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ROM Verification Characteristics = 25 ˚C 5 ˚ – Parameter Symbol ROM Verification Mode 1 (Standard Verify Mode for not Read Protected ROM) Address to valid data ...
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ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM) ROM Verification Mode 2 Semiconductor Group SAB 80C515A/83C515A-5 6-54 ...
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Application Example for Verifying the Internal ROM with ROM Verify Mode 2 Semiconductor Group SAB 80C515A/83C515A-5 6-55 ...
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AC Inputs during testing are driven at V ments are made at V for a logic ’1’ and V IHmin AC Testing: Input, Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change ...