LPC47N267_05 SMSC [SMSC Corporation], LPC47N267_05 Datasheet

no-image

LPC47N267_05

Manufacturer Part Number
LPC47N267_05
Description
100 Pin LPC Super I/O with X-Bus Interface
Manufacturer
SMSC [SMSC Corporation]
Datasheet
PRODUCT FEATURES
SMSC LPC47N267
3.3 Volt Operation (5V tolerant)
Programmable Wakeup Event Interface
SMI Support (IO_SMI# Pin)
GPIOs (29)
Four IRQ Input Pins
X-Bus Interface
XNOR Chain
PC99 and ACPI 1.0b Compliant
100-pin STQFP Package
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
Floppy Disk Available on Parallel Port Pins (ACPI
Enhanced Digital Data Separator
(IO_PME# Pin)
— Supports up to 4 external components
— Supports I/O cycles (No Memory Support)
— 8-Bit Data Transfer
— 6-Bit Address Qualification
— Write Protection for each component
— Licensed CMOS 765B Floppy Disk Controller
— Software and Register Compatible with SMSC's
— Supports One Floppy Drive Directly
— Configurable Open Drain/Push-Pull Output Drivers
— Supports Vertical Recording Format
— 16-Byte Data FIFO
— 100% IBM Compatibility
— Detects All Overrun and Underrun Conditions
— Sophisticated Power Control Circuitry (PCC) Including
— DMA Enable Logic
— Data Rate and Drive Control Registers
— Swap Drives A and B
— Non-Burst Mode DMA Option
— 48 Base I/O Address, 15 IRQ and 3 DMA Options
— Forceable Write Protect and Disk Change Controls
Compliant)
— 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data
— Programmable Precompensation Modes
Proprietary 82077AA Compatible Core
Multiple Powerdown Modes for Reduced Power
Consumption
Rates
PRODUCT PREVIEW
Serial Ports
Infrared Communications Controller
Multi-Mode Parallel Port with ChiProtect
LPC Bus Host Interface
Mechanical Package
— Two Full Function Serial Ports
— High Speed NS16C550 Compatible UARTs with
— Supports 230k and 460k Baud
— Programmable Baud Rate Generator
— Modem Control Circuitry
— IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR
— 2 IR Ports
— 96 Base I/O Address, 15 IRQ Options and 3 DMA
— Standard Mode IBM PC/XT, PC/AT, and PS/2
— Enhanced Parallel Port (EPP) Compatible - EPP 1.7
— IEEE 1284 Compliant Enhanced Capabilities Port
— ChiProtect Circuitry for Protection Against Damage Due
— 192 Base I/O Address, 15 IRQ and 3 DMA Options
— Multiplexed Command, Address and Data Bus
— 8-Bit I/O Transfers
— 8-Bit DMA Transfers
— 16-Bit Address Qualification
— Serial IRQ Interface Compatible with Serialized IRQ
— PCI nCLKRUN Support
— Power Management Event (IO_PME#) Interface Pin
— 100 pin STQFP (12mm x 12mm body size)
LPC47N267
100 Pin LPC Super I/O
with X-Bus Interface
Send/Receive 16-Byte FIFOs
Support
Options
Compatible Bidirectional Parallel Port
and EPP 1.9 (IEEE 1284 Compliant)
(ECP)
to Printer Power-On
Support for PCI Systems
Revision 01-03-05
Data Brief

Related parts for LPC47N267_05

LPC47N267_05 Summary of contents

Page 1

PRODUCT FEATURES 3.3 Volt Operation (5V tolerant) Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (29) Four IRQ Input Pins X-Bus Interface — Supports external components — Supports I/O cycles (No Memory Support) — ...

Page 2

ORDER NUMBER(S): LPC47N267-MN FOR 100 PIN, STQFP PACKAGE 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2005 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included ...

Page 3

Pin LPC Super I/O with X-Bus Interface General Description The SMSC LPC47N267 and ACPI 1.0 compliant Super I/O Controller. The LPC47N267 implements an LPC interface, a pin reduced ISA interface, for supported I/O and ...

Page 4

Block Diagram nIO_SMI* SMI PME WDT XD[0:7]* XCS0#* XCS1#* X-BUS XCS2#* INTERFACE XRD#* XWR#* XA0* XA1* XA2* XA3/XCS3#* SER_IRQ SERIAL IRQ PCI_CLK LAD0 LAD1 LAD2 LPC BUS INTERFACE LAD3 nLFRAME nLDRQ nPCI_RESET nLPCPD nCLKRUN CLOCK GEN CLOCKI V Vcc Vss ...

Page 5

Pin LPC Super I/O with X-Bus Interface Package Outline Figure 2 100 Pin STQFP, 12X12X1.4 Body, 2.0 MM Footprint Table 1 100 Pin STQFP Package Parameters MIN NOMINAL 0. 1.35 1.40 D 13.80 ...

Related keywords