DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 64

• Manufacturer Part Number: DZPD6722VCCE
• Description: ISA-to-PC-Card (PCMCIA) Controllers
• Manufacturer: INTEL [Intel Corporation]

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
9.0
9.1
64
Register Name: System Memory Map 0–4 Start Address Low
Index: 10h, 18h, 20h, 28h, 30h
Bit 7
Memory Window Mapping Registers
The following information about the memory map windows is important:
System Memory Map 0–4 Start Address Low
There are five separate System Memory Map Start Address Low registers, each with identical
fields. These registers are located at the following indexes:
•
•
•
•
•
Bit 6
The memory window mapping registers determine where in the ISA memory space and PC
Card memory space accesses will occur. There are five memory windows that can be used
independently.
The memory windows are enabled and disabled using the Mapping Enable register (see
“Mapping Enable” on page
To specify where in the ISA space a memory window is mapped, start and end addresses are
specified. A memory window is selected whenever the appropriate Memory Map Enable bit
(see
appropriate System Memory Map Start Address register (see
Start Address Low” on page
System Memory Map End Address register (see
Low” on page
Start and end addresses are specified with ISA Address bits 23:12. This sets the minimum size
of a memory window to 4K bytes. Memory windows are specified in the ISA address from 64
Kbytes to 16 Mbytes (0010000h–FFFFFFh). Note that no memory window can be mapped in
the first 64 Kbytes of the ISA address space.
To ensure proper operation, none of the windows can overlap in the ISA address space.
Index
10h
18h
20h
28h
30h
“Mapping
Bit 5
System Memory Map Start Address Low
System Memory Map 0 Start Address Low
System Memory Map 1 Start Address Low
System Memory Map 2 Start Address Low
System Memory Map 3 Start Address Low
System Memory Map 4 Start Address Low
66).
Enable”) is set, and when the ISA address is greater than or equal to the
Bit 4
55).
Start Address 19:12
64) and the ISA address is less than or equal to the appropriate
RW:00000000
Bit 3
“System Memory Map 0–4 End Address
Bit 2
“System Memory Map 0–4
Register Compatibility Type: 365
Bit 1
Register Per: socket
Datasheet
Bit 0