AT89C51CC02CA-TDSUM ATMEL [ATMEL Corporation], AT89C51CC02CA-TDSUM Datasheet - Page 128

• Manufacturer Part Number: AT89C51CC02CA-TDSUM
• Description: Enhanced 8-bit Microcontroller with CAN Controller and Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Voltage Conversion
Clock Selection
Figure 54. A/D Converter Clock
ADC Standby Mode
128
AT/T89C51CC02
CPU Core Clock Symbol
CLOCK
CPU
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Table 102. Selected Analog input
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range (See section
“AC-DC”).
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres-
caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
if PRS = 0 then F
if PRS > 0 then F
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN
in ADCON register. In this mode the power dissipation is reduced.
÷
2
SCH2
0
0
0
0
1
1
1
1
ADC
ADC
= F
= F
periph
periph
Prescaler ADCLK
/ 64
/ 2 x PRS
SCH1
0
0
1
1
0
0
1
1
ADC Clock
SCH0
0
1
0
1
0
1
0
1
Converter
A/D
Selected Analog Input
4126J–CAN–05/06
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7