ISL6313 INTERSIL [Intersil Corporation], ISL6313 Datasheet - Page 22

• Manufacturer Part Number: ISL6313
• Description: Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

to the final DAC voltage is referred to as tDB, and can be
calculated as shown in Equation 22:
At the end of soft-start, PGOOD will immediately go high if
the VSEN voltage is within the undervoltage and overvoltage
limits.
Pre-Biased Soft-Start
The ISL6313 also has the ability to start up into a pre-charged
output, without causing any unnecessary disturbance. The FB
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off. Once the internal ramping
reference exceeds the FB pin potential, the output drives are
enabled, allowing the output to ramp from the pre-charged
level to the final level dictated by the DAC setting. Should the
output be pre-charged to a level exceeding the DAC setting,
tDB
GND>
GND>
FIGURE 15. SOFT-START WAVEFORMS FOR ISL6313-BASED
=
V
OUTPUT PRECHARGED
VID
BELOW DAC LEVEL
FIGURE 14. SOFT-START WAVEFORMS
⋅
OUTPUT PRECHARGED
R
MULTI-PHASE CONVERTER
ABOVE DAC LEVEL
SS
tDA
V
OUT
T1
⋅
PGOOD
8 10
T2
, 500mV/DIV
EN
⋅
–
3
(
μs
500µs/DIV
22
)
tDB
T3
V
OUT
EN (5V/DIV)
(0.5V/DIV)
(EQ. 22)
ISL6313
the output drives are enabled at the end of the soft-start
period, leading to an abrupt correction in the output voltage
down to the DAC-set level.
Fault Monitoring and Protection
The ISL6313 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 16
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6313 is regulating the
output voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied through a resistor to
a voltage source that’s equal to or less then VCC.
For Intel mode of operation, PGOOD indicates whether VSEN
is within specified overvoltage and undervoltage limits after a
fixed delay from the end of soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
EN, POR, or one of the no-CPU VID codes. In the event of
an overvoltage or overcurrent condition, or a no-CPU VID
code, the controller latches off and PGOOD will not return
high until EN is toggled and a successful soft-start is
FIGURE 16. POWER GOOD AND PROTECTION CIRCUITRY
SS
VSEN
VDAC + RGND
100µA
I
1.260V
AVG
VDAC + RGND
+175mV
+225mV
OR
-350mV
+
-
OCP
+
+
-
-
OVP
AND CONTROL LOGIC
UV
SOFT-START, FAULT
ISL6313 INTERNAL CIRCUITRY
EACH CHANNEL
OCL
REPEAT FOR
OCP
+
-
+
-
140µA
I
1
V
March 5, 2007
PGOOD
OCP
IOUT
FN6448.0