ISL6313 INTERSIL [Intersil Corporation], ISL6313 Datasheet - Page 29

• Manufacturer Part Number: ISL6313
• Description: Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f
higher if desired. Choosing f
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 42, R
compensation components are then selected according to
Equation 42.
In Equation 42, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
peak sawtooth signal amplitude as described in the
Electrical Specifications on page 6.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
R
C
C
R
C
1
1
2
C
C
=
=
=
=
=
R
------------------------------------------- -
--------------------------------------------------------------------------------------------------- -
(
---------------------------------------------------------------------------------------- -
--------------------------------------------------------------------------------------------------- -
(
V
2 π
2 π
FB
L C
PP
⋅
⋅
⋅
V
⋅
IN
)
⋅
V
)
R
2
------------------------------------------- -
2
–
⎛
⎝
IN
2π
L C
FB
⋅
⋅
⋅
C ESR
f
(
f
⋅
0
2 π f
⋅
0
FB
⎞
⎠
C ESR
⋅
(
⋅
2
⋅
⋅
2 π f
f
⋅
f
–
HF
⋅
HF
is selected arbitrarily. The remaining
⋅
f
C ESR
⋅
0
⋅
HF
⋅
⋅
⋅
⋅
V
(
f
(
IN
HF
HF
⋅
L C
L C
⋅
⋅
⋅
⋅
L C
L C R
⋅
L C
HF
⋅
) R
) R
29
⋅
⋅
⋅
–
⋅
to be lower than 10f
HF
1
FB
FB
–
)
1
FB
)
= 10f
⋅
⋅
V
V
PP
PP
PP
0
, but it can be
is the peak-to-
MAX
0
(EQ. 42)
can
.
ISL6313
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I
capacitors are selected, the maximum allowable ripple
voltage, V
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 45 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 46
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
ΔV ESL
L
L
≤
≥
MAX
≈
2 N C V
---------------------------------
ESR
⋅
(
. This places an upper limit on inductance.
ΔI
⋅
⋅
⋅
PP(MAX)
)
⎛
⎝
------------------------------------------------------------------- -
---- -
dt
2
di
V
⋅
IN
f
+
O
S
ESR ΔI
–
⋅
⋅
MAX
V
N V
ΔV
IN
, determines the lower limit on the
⋅
⋅
⋅
.
MAX
OUT
V
PP MAX
C(PP)
–
⎞ V
⎠
(
(
⋅
ΔI ESR
OUT
⋅
(ESR). Thus, once the output
)
)
March 5, 2007
(EQ. 45)
(EQ. 43)
(EQ. 44)
FN6448.0