CS8405A-IZ CIRRUS [Cirrus Logic], CS8405A-IZ Datasheet - Page 18

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CS8405A-IZ

Manufacturer Part Number
CS8405A-IZ
Description
96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
8.2
8.3
The Data Flow Control register configures the flow of audio data. The output data should be muted prior to changing
bits in this register to avoid transients.
18
7
7
0
0
Control 2 (2h)
Data Flow Control (3h)
MMT - Select AES3 transmitter mono or stereo operation
MMTCS - Select A or B channel status data to transmit in mono mode
MMTLR - Channel Selection for AES Transmitter mono mode
TXOFF - AES3 Transmitter Output Driver Control
AESBP - AES3 bypass mode selection
Default = ‘0’
0 - Normal stereo operation
1 - Output either left or right channel inputs into consecutive subframe outputs (mono
Default = ‘0’
0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe
1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the
Default = ‘0’
0 - Use left channel input data for consecutive subframe outputs
1- Use right channel input data for consecutive subframe outputs
Default = ‘0
0 - AES3 transmitter output pin drivers normal operation
1 - AES3 transmitter output pin drivers drive to 0 V.
Default = ‘0’
0 - Normal operation
1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL
mode, left or right is determined by MMTLR bit)
left channel CS data. If MMTLR = 1, use the right channel CS data.
threshold digital input.
TXOFF
6
6
0
AESBP
5
5
0
4
0
4
0
3
0
3
0
MMT
2
2
0
MMTCS
1
1
0
CS8405A
DS469PP4
MMTLR
0
0
0

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