CS8405A-IZ CIRRUS [Cirrus Logic], CS8405A-IZ Datasheet - Page 25

• Manufacturer Part Number: CS8405A-IZ
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

DS469PP4
INT
U
OMCK
H/S
TXN
TXP
AD1/CDIN
SCL/CCLK
19
20
21
24
25
26
27
28
Interrupt (Output) - Indicates key events during the operation of the CS8405A. All bits affecting INT
may be unmasked through bits in the control registers. Indication of the condition(s) that initiated an
interrupt are readable in the control registers. The polarity of the INT output, as well as selection of a
standard or open drain output, is set through a control register. Once set true, the INT pin goes false
only after the interrupt status registers have been read and the interrupt status bits have returned to
zero.
User Data (Input/Output) - May optionally be used to input User data for transmission by the AES3
transmitter, see Figure 7 for timing information. Alternatively, the U pin may be set to output, which also
selects the internal buffer as the source of transmitted U data. If not driven, a 47 kΩ pull-down resistor is
recommended for the U pin, because the default state of the UD direction bit sets the U pin as an input.
The pull-down resistor ensures that the transmitted user data will be zero. If the U pin is always set to be
an output, thereby causing the U bit manager to be the source of the U data, then the resistor is not nec-
essary. The U pin should not be tied directly to ground, in case it is programmed to be an output, and
subsequently tries to output a logic high. This situation may affect the long term reliability of the device.
If the U pin is driven by a logic level output, then a 100 Ω series resistor is recommended.
Master Clock (Input) - The frequency must be 256x, 384x, or 512x the sample rate.
Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation
of the CS8405A, and the method of accessing Channel Status and User bit data. In software mode,
device control and CS and U data access is primarily through the control port, using a microcontroller.
Hardware mode provides an alternate mode of operation, and access to CS and U data is provided by
dedicated pins. This pin should be permanently tied to VL+ or DGND.
Differential Line Drivers (Output) - Transmitting AES3 data. Drivers are pulled low while the CS8405A
is in the reset state.
Address Bit 1 (Two-Wire Mode) / Serial Control Data in (SPI) (Input) - In Two-Wire mode, AD1 is a
chip address pin. In SPI mode, CDIN is the input data line for the control port interface.
Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8405A. In Two-Wire mode, SCL requires an external pull-up resistor to VL+.
CS8405A
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