CS8405A-IZ CIRRUS [Cirrus Logic], CS8405A-IZ Datasheet - Page 19

• Manufacturer Part Number: CS8405A-IZ
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

8.4
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
8.5
DS469PP4
SIMS
7
0
7
Clock Source Control (4h)
Serial Audio Input Port Data Format (5h)
RUN - Controls the internal clocks, allowing the CS8405A to be placed in a “powered down” low
current consumption, state.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector.
If these bits are changed during normal operation, then always stop the CS8405A first (RUN = 0),
write the new value, then start the CS8405A (RUN = 1).
SIMS - Master/Slave Mode Selector
SISF - ISCLK frequency (for master mode)
SIRES1:0 - Resolution of the input data, for right-justified formats
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
1 - Normal part operation. This bit must be set to 1 to allow the CS8405A
Default = ‘00’
00 - OMCK frequency is 256*Fs
01 - OMCK frequency is 384*Fs
10 - OMCK frequency is 512*Fs
11 - Reserved
Default = ‘0’
0 - Serial audio input port is in slave mode
1 - Serial audio input port is in master mode
Default = ‘0’
0 - 64*Fs
1 - 128*Fs
Default = ‘00’
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Reserved
control port registers are operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
RUN
SISF
6
6
SIRES1
CLK1
5
5
SIRES0
CLK0
4
4
SIJUST
3
0
3
SIDEL
2
2
0
SISPOL
1
1
0
CS8405A
SILRPOL
0
0
0
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