74AC109_07 FAIRCHILD [Fairchild Semiconductor], 74AC109_07 Datasheet

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74AC109_07

Manufacturer Part Number
74AC109_07
Description
Dual JK Positive Edge-Triggered Flip-Flop
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
74AC109, 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
FACT™ is a trademark of Fairchild Semiconductor Corporation
74AC109SC
74AC109SJ
74AC109MTC
74ACT109SC
74AC109MTC
74ACT109PC
I
Outputs source/sink 24mA
ACT109 has TTL-compatible inputs
CC
Number
Order
reduced by 50%
Package
Number
MTC16
MTC16
M16A
M16D
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
.
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
Pin Descriptions
J
CP
C
S
Q
1
– LOW input to S
– LOW input to C
– Clear and Set are independent of clock
– Simultaneous LOW on C
D1
D1
1
Package Description
, J
, Q
1
Q and Q HIGH
, S
, C
, CP
2
Pin Names
, K
2
D2
D2
, Q
1
2
, K
1
, Q
2
2
D
D
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
D
and S
Description
D
makes both
www.fairchildsemi.com
March 2007
tm

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74AC109_07 Summary of contents

Page 1

Dual JK Positive Edge-Triggered Flip-Flop Features ■ I reduced by 50% CC ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs Ordering Information Order Package Number Number 74AC109SC M16A 74AC109SJ M16D 74AC109MTC MTC16 74ACT109SC M16A 74AC109MTC MTC16 74ACT109PC ...

Page 2

Logic Symbols Truth Table Each half HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial ) = Previous ...

Page 3

Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure ...

Page 4

DC Electrical Characteristics for AC Symbol Parameter V Minimum HIGH IH Level Input Voltage V Maximum LOW IL Level Input Voltage V Minimum HIGH OH Level Output Voltage V Maximum LOW OL Level Output Voltage (3) I Maximum Input IN ...

Page 5

DC Electrical Characteristics for ACT Symbol Parameter V Minimum HIGH IH Level Input Voltage V Maximum LOW IL Level Input Voltage V Minimum HIGH OH Level Output Voltage V Maximum LOW OL Level Output Voltage I Maximum Input IN Leakage ...

Page 6

AC Electrical Characteristics for AC Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay, PLH Propagation Delay, PHL Propagation Delay, t PLH ...

Page 7

AC Electrical Characteristics for ACT Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay, PLH Propagation Delay, PHL Propagation Delay, PLH ...

Page 8

Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 Package Number M16A 8 www.fairchildsemi.com ...

Page 9

Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 Package Number M16D 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.00±0.10 4.55 0.11 MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 0.65 4.4±0.1 1.45 Package Number ...

Page 11

Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 Package Number N16E 11 www.fairchildsemi.com ...

Page 12

TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world. ActiveArray Bottomless Build ...

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