74GTL1655ATTR STMICROELECTRONICS [STMicroelectronics], 74GTL1655ATTR Datasheet

no-image

74GTL1655ATTR

Manufacturer Part Number
74GTL1655ATTR
Description
16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
DESCRIPTION
The 74GTL1655A devices are 16-bit high-drive
(100mA), low-output-impedance universal bus
transceivers designed for backplane applications.
The 74GTL1655A devices provide live-insertion
capability for backplane applications by tolerating
active signals on the data ports when the devices
are powered off. In addition, a biasing pin
preconditions the GTL/GTL+ port to minimize
disruption to an active backplane.
The edge rate-control (V
the rise and fall time of the B outputs can be
configured to optimize for various backplane
loading conditions. Data flow in each direction is
October 2004
HIGH SPEED GTL/GTL+ UNIVERSAL
TRANSCEIVER:
t
COMBINES D-TYPE LATCHES AND D-TYPE
FLIP-FLOPS FOR OPERATION IN
TRANSPARENT, LATCHED, OR CLOCKED
MODE
OPERATING VOLTAGE RANGE:
V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OUTPUT IMPEDANCE:
I
HIGH-IMPEDANCE STATE DURING POWER
UP AND POWER DOWN up to
V
INSERTION
B-PORT PRECHARGED BY BIASV
REDUCE NOISE ON THE LINE DURING
LIVE INSERTION
EDGE RATE-CONTROL INPUT
CONFIGURES THE B-PORT OUTPUT RISE
AND FALL TIMES
BUS HOLD ON DATA INPUTS ELIMINATES
THE NEED FOR EXTERNAL PULL-UP/
PULL-DOWN RESISTORS (A PORT)
DISTRIBUTED V
CONFIGURATION MINIMIZES HIGH-SPEED
SWITCHING NOISE IN PARALLEL
COMUNICATIONS
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 1655
PD
OL
OH
CC
CC
= 4.6 ns (MAX.) A to B at V
= 100mA (MIN) at V
| = I
(OPR) = 3.0V to 3.6V
=BIASV
OL
=24mA (MIN) at V
CC
=1.5V PERMITT LIVE
CC
AND GND PIN
ERC
16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS
CC
) input is provided so
= 3V (B PORT)
CC
CC
= 3V (A PORT)
TRANSCEIVERS WITH LIVE INSERTION
= 3V
CC
Table 1: Order Codes
Figure 1: Pin Connection
PACKAGE
TSSOP
TSSOP
74GTL1655A
74GTL1655ATTR
Rev. 1
T & R
1/16

Related parts for 74GTL1655ATTR

74GTL1655ATTR Summary of contents

Page 1

... B outputs can be configured to optimize for various backplane loading conditions. Data flow in each direction is October 2004 TRANSCEIVERS WITH LIVE INSERTION = 3V CC Table 1: Order Codes = 3V (A PORT PORT) Figure 1: Pin Connection CC 74GTL1655A TSSOP PACKAGE T & R TSSOP 74GTL1655ATTR Rev. 1 1/16 ...

Page 2

OEBA), latch-enable (LEAB and LEBA), and clock (CLK) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if ...

Page 3

Table 3: Function Table (1) OEAB LEAB data flow is shown flow is similar, but uses OEBA, LEBA and ...

Page 4

Figure 3: Logic Diagram 4/16 ...

Page 5

Table 6: Absolute Maximum Ratings Symbol V Supply Voltage, Bias Input Voltage A Side, Control Input Input Voltage B Side Output Voltage A Side Output Voltage ...

Page 6

Table 8: DC Specifications Symbol Parameter V High Level Input Voltage IK V High Level Output OHA Voltage A Port V Low Level Output OLA Voltage A Port V Low Level Output OLB Voltage B Port I Input Current ...

Page 7

Table 9: Live Insertion Specifications Symbol Parameter I (Bias Quiescent Bias Current Output Voltage B Port O I Output Current B Port O Table 10: AC Electrical Characteristics for GTL (V =3.3 0.3V, V =1.2V, ...

Page 8

Symbol Parameter t Enable Delay Time EN OEBA Disable Delay Time DIS OEBA Set-up Time SU t Hold Time H t Pulse duration W Slew rate Slew rate B output ...

Page 9

Symbol Parameter t Propagation Delay Time PLH PHL t Propagation Delay Time PLH PHL t Propagation Delay Time PLH LEBA PHL t Enable Delay Time EN OEBA or ...

Page 10

Table 12: Test Circuit For "B" Outputs C = 30pF or equivalent (includes jig and probe capacitance 12.5 or equivalent pulse generator (typically OUT t =t ...

Page 11

Figure 7: Waveform - Clock To A Port Propagation Delay Time Figure 8: Waveform - Setup And Hold Time 74GTL1655A 11/16 ...

Page 12

Figure 9: Waveform - Enable And Disable Time (A Port) 12/16 ...

Page 13

TSSOP64 MECHANICAL DATA DIM. MIN 0. 0.17 c 0. 6.0 e 0.5 BSC K 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. MIN. 1.1 0.15 0.002 ...

Page 14

Tape & Reel TSSOP64 MECHANICAL DATA DIM. MIN 12 8.7 Bo 17.2 Ko 1.4 Po 3.9 P 11.9 14/16 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.342 ...

Page 15

Table 13: Revision History Date Revision 18-Oct-2004 1 Description of Changes First Release. 74GTL1655A 15/16 ...

Page 16

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...

Related keywords