AT88SA102S_10 ATMEL [ATMEL Corporation], AT88SA102S_10 Datasheet - Page 12

• Manufacturer Part Number: AT88SA102S_10
• Description: Atmel CryptoAuthentication
• Manufacturer: ATMEL [ATMEL Corporation]

4.2.
4.3.
4.4.
4.4.1. IO Timeout
12
IO Blocks
Commands are sent to the chip, and responses received from the chip, within a block
following way:
IO Flow
The general IO flow for the MAC command is as follows:
1. System sends Wake token
2. System sends Transmit flag
3. Receive 0x11 value from the Atmel
4. System sends Command flag
5. System sends complete command block
6. System waits t
7. System sends Transmit flag. If command format is OK, the AT88SA102S ignores this flag because the
8. System waits t
9. System sends Transmit flag
10. Receive output block from the AT88SA102S, system checks CRC
11. If CRC from the AT88SA102S is incorrect, indication transmission error, system resends Transmit flag
12. System sends sleep flag to the AT88SA102S
All commands other than MAC have a short execution delay. In these cases, the system should omit steps six,
seven and eight and replace this with a wait of duration t
Synchronization
Because the communications protocol is half duplex, there is the possibility that the system and AT88SA102S will
fall out of synchronization with each other. In order to speed recovery, AT88SA102S implements a timeout that
forces the chip to sleep.
After a leading transition for any data token has been received, AT88SA102S will expect the remaining bits of the
token to be properly received by the chip within the t
transmission of an illegal token (a low pulse exceeding t
t
The same timeout applies during the transmission of the command block. After the transmission of a legal
command flag, the IO Timeout circuitry is enabled until the last expected data bit is received.
Atmel AT88SA102S
TIMEOUT
Byte
0
1 to (N-2)
N-1, N
computation engine is busy. If there was an error, the AT88SA102S responds with an error code
interval.
The timeout counter is reset after every legal token, so the total time to transmit the command may exceed the
t
TIMEOUT
Name
Count
Packet
Checksum
interval while the time between bits may not.
PARSE
EXEC
, refer to Section
for the AT88SA102S to check for command formation errors
Meaning
Number of bytes to be transferred to the chip in the block, including count, packet and
checksum, so this byte should always have a value of (N+1). The maximum size block is 39
and the minimum size block is 4. Values outside this range will cause unpredictable operation.
Command, parameters and data, or response. Refer to Section
details.
CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial
register value should be 0 and after the last bit of the count and packet have been transmitted
the internal CRC register should have a value that matches that in the block. The first byte
transmitted (N-1) is the least significant byte of the CRC value so the last byte of the block is
the most significant byte of the CRC.
®
4.1.1
AT88SA102S to verify proper wakeup synchronization
PARSE
ZLO
TIMEOUT
) will cause the chip to enter the sleep state after the
+ t
EXEC
interval. Failure to send enough bits or the
.
4.1.2
that is constructed in the
and Section
5
8584F–SMEM–8/10
for more